Channel Isolation Structure for Semiconductor Leakage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The continuous scaling down of semiconductor device dimensions and increasing demand for higher performance lead to challenges such as increased metal gate extrusion defects and S/D epi pit defects due to sloped sidewalls in fin structures, which affect gate control and leakage current.
Innovation Solution
A method is introduced to form an isolation layer surrounding a sloped portion of a channel structure in semiconductor devices, where a first isolation layer is formed on the substrate, the channel structure is trimmed to create sloped and vertical sidewall surfaces, and a second isolation layer is applied to cover the sloped surfaces, allowing a gate structure to be formed with substantially vertical sidewall surfaces without gate footing, thereby improving gate control and reducing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the dimensions of semiconductor devices are scaled down to increase storage capacity and processing speed, then higher performance and storage capacity are achieved, but manufacturing complexity and process control difficulty increase
Solution Approach 1:
The patent segments the sidewall surface into two distinct zones: a first region with a first sidewall surface and a second region with a second sidewall surface having a different angle. This segmentation allows each region to be optimized independently for its specific function, enabling continued device scaling while maintaining manufacturability through region-specific process control.
Solution Approach 2:
The patent applies local quality by creating different sidewall surface characteristics in different regions. The first region has one sidewall angle optimized for certain electrical properties, while the second region has a different sidewall angle optimized for other properties. This local differentiation resolves the contradiction by allowing complex functionality to be achieved through localized structural variations rather than uniform complex structures throughout.
2Ease of manufacture
If sloped sidewalls are used in fin structures, then manufacturing is simplified, but metal gate extrusion defects and S/D epi pit defects increase
Solution Approach 1:
The patent creates a structure where the first region has a first sidewall surface with a first angle and the second region has a second sidewall surface with a second angle. This local quality differentiation allows the sidewalls to provide the necessary structural support and processability benefits while the specific angular variations prevent the uniform sloped sidewalls that cause gate extrusion and epi pit defects.
Solution Approach 2:
By dividing the sidewall structure into distinct regions with different angular characteristics, the patent segments the potential defect-prone uniform slope into controlled zones. This segmentation allows each region to contribute positively to manufacturing ease while collectively preventing the defect formation that occurs with continuous sloped sidewalls.
3Ease of manufacture
If gate footing is present in the gate structure, then manufacturing is easier, but gate control and leakage current performance deteriorate
Solution Approach 1:
The segmented sidewall structure with different angular regions enables precise control over the gate formation process. The specific configuration of first and second sidewall surfaces guides the gate material deposition and shaping processes to naturally form vertical sidewalls without footing, achieving both ease of manufacture through self-alignment and high precision in gate control.
Solution Approach 2:
The patent performs preliminary action by pre-forming the channel structure with specific sidewall angles before gate formation. This preliminary structuring of the first and second regions with their respective sidewall angles creates a template that guides subsequent gate processing to produce vertical sidewalls automatically, eliminating the need for corrective footing removal steps and ensuring precise gate control from the outset.
Data Source
AI summary
The present disclosure describes forming a semiconductor structure having an isolation layer surrounding a sloped portion of a channel structure. The semiconductor structure includes a channel structure having first, second, and third portions on a substrate. The first portion has a first width. The second portion has a second width less than the first width. The third portion has a third width less than the second width. The semiconductor structure further includes a first isolation layer on the substrate and surrounding the first portion, a second isolation layer on the first isolation layer and surrounding the second portion of the channel structure, and a gate structure on the second isolation layer and surrounding the third portion of the channel structure.