Channel Isolation Structure for Dense Multi-Gate Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices shrink in pitch, there is a need to decrease capacitance and ensure electrical stability between contacts, while also effectively suppressing short channel effects in multi-gate transistors.
Innovation Solution
The semiconductor device incorporates a lower pattern with sidewalls, a channel isolation structure contacting one sidewall, a field insulating layer contacting the opposite sidewall, and a gate structure disposed on the lower pattern, contacting the channel isolation structure. The channel isolation structure has varying widths in different regions, with a specific configuration to enhance electrical stability and capacitance control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch of the semiconductor device is decreased to increase circuit density, then the device density is improved, but the capacitance between contacts increases and electrical stability deteriorates
Solution Approach 1:
The channel isolation structure is divided into multiple regions (first region, second region, third region) with different width characteristics. The first region has a constant width, the second region has a width that increases as distance from the bottom surface increases, and the third region has a constant width greater than the first region. This segmentation allows different portions of the isolation structure to serve different functions: electrical isolation, mechanical support, and capacitance control, thereby resolving the contradiction between high density and electrical stability.
Solution Approach 2:
Different regions of the channel isolation structure are given different local properties. The second region specifically has increasing width with height to control capacitance between contacts, while other regions maintain constant widths for isolation purposes. This local differentiation of structural properties enables the device to achieve both high circuit density and maintained electrical stability despite pitch reduction.
2Reliability
If the gate length of the multi-gate transistor is increased to suppress short channel effects, then the short channel effect is suppressed, but the scaling capability is reduced
Solution Approach 1:
The patent transitions from planar channel isolation to three-dimensional multi-gate transistor structures with channels extending in multiple directions (fin-shaped, nanowire-shaped, or nanosheet channels). The channel isolation structure extends in a first direction while gate electrodes wrap around channels from multiple sides. This dimensional transformation enables effective short channel effect suppression through enhanced gate control in three dimensions without requiring increased gate length, thereby maintaining scaling capability.
3Reliability
If the width of the channel isolation structure is increased to improve electrical stability, then the electrical stability is improved, but the device area increases
Solution Approach 1:
The channel isolation structure employs dynamic width variation along its height rather than a uniform width. The second region has a width that increases as distance from the bottom surface increases, creating a tapered profile. This dynamic dimensional change allows the structure to provide enhanced electrical stability and capacitance control in the upper regions where contacts are located, while maintaining a smaller footprint at the base, thereby avoiding excessive device area expansion.
Data Source
AI summary
A semiconductor device includes a lower pattern. A channel isolation structure and a field insulating layer contact the lower pattern. A gate structure is on the lower pattern, in contact with the channel isolation structure. A channel pattern is on the lower pattern, and includes sheet patterns, each being in contact with the channel isolation structure. A source/drain pattern contacts the channel pattern and the channel isolation structure. The channel isolation structure includes a first region contacting the gate structure and a second region contacting the source/drain pattern. The second region of the channel isolation structure includes portions whose widths increase as a distance from a bottom surface of the field insulating layer increases. A width of an uppermost portion of the channel isolation structure is greater than a width of a lowermost portion of the channel isolation structure