Semiconductor Channel Layer Segmentation for Mixed-Power Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, making it hard to maintain production efficiency and lower costs while ensuring device reliability.
Innovation Solution
The method involves forming blocking dielectrics on opposite sides of the bottommost semiconductor layer and replacing it to reduce the number of channel layers in transistors, allowing for customization of transistors with different channel layers on different regions of a substrate, enabling either high current or low power consumption applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency and cost are improved, but fabrication process complexity and difficulty increase
Solution Approach 1:
The patent divides the semiconductor device into distinct regions (first region and second region) with different transistor configurations. This segmentation allows different fabrication processes to be applied to different regions, simplifying the overall fabrication complexity while maintaining high functional density through regional optimization rather than uniform miniaturization across the entire device.
Solution Approach 2:
The patent implements local quality by creating transistors with different numbers of channel layers in different regions of the substrate. The first region contains transistors with a first number of channel layers optimized for high current applications, while the second region contains transistors with a second number of channel layers optimized for low power consumption applications. This regional differentiation allows each region to be fabricated with appropriate process complexity levels.
2Productivity
If feature sizes are decreased to increase functional density, then more devices per chip area are achieved, but device reliability becomes harder to maintain
Solution Approach 1:
The patent ensures device reliability by optimizing transistor structure locally for different application requirements. High current transistors use a specific number of channel layers configured for current handling, while low power transistors use a different configuration optimized for power efficiency. This local optimization maintains reliability by preventing the use of inappropriate transistor configurations that would result from uniform miniaturization.
3Adaptability or versatility
If transistors are customized for different applications (high current vs low power), then application-specific performance is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the substrate into distinct fabrication regions where different transistor types are created. This allows customization for different applications (high current vs low power) while managing manufacturing complexity through regionalization rather than requiring complex multi-step processes for each individual transistor across the entire wafer.
Solution Approach 2:
The patent achieves application-specific customization through local quality by configuring transistors in the first region for high current applications with appropriate channel layer structures, while transistors in the second region are configured for low power consumption applications. This regional differentiation enables tailored performance characteristics without requiring complex customization processes for each device.
Data Source
AI summary
A method includes forming first semiconductor layers vertically stacked over a substrate; forming a gate structure over the first semiconductor layers; etching portions of the first semiconductor layers and the substrate uncovered by the substrate to form recesses; forming a spacer layer covering sidewalls of portions of the first semiconductor layers, while a bottommost one of the first semiconductor layers is uncovered by the spacer layer; etching the bottommost one of the first semiconductor layers to form a gap; forming a blocking dielectric in the gap; and forming source/drain epitaxy structures in the recesses and on opposite sides of the gate structure.