Memory Cell Channel Layer Doping for Lower Threshold Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The mobility of the channel semiconductor layer in semiconductor memory devices is limited by its high threshold voltage, leading to increased operation voltage, which affects the performance of memory cells.
Innovation Solution
Incorporating a specific concentration of metal atoms, such as nickel, into the channel semiconductor layer, which are deposited on its surface and then diffused in to crystallize the layer at a lower temperature, increasing the particle diameter of crystal grains and reducing the threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel semiconductor layer is formed with conventional methods, then the manufacturing process is simple, but the mobility is limited due to high threshold voltage
Solution Approach 1:
The patent changes the chemical composition parameter of the channel semiconductor layer by incorporating metal atoms (such as nickel) at specific concentrations (1×10^19 to 1×10^21 atoms/cm³). This parameter change enables the layer to be formed at lower temperatures while achieving higher mobility and lower threshold voltage, thus improving reliability without excessively complicating the manufacturing process
Solution Approach 2:
The patent creates a composite semiconductor layer by combining silicon with metal atoms (nickel, cobalt, or copper). This composite structure allows the channel layer to achieve both low threshold voltage and high mobility, resolving the contradiction between simple manufacturing and high performance
2Reliability
If metal atoms are incorporated to reduce threshold voltage, then mobility increases, but leakage currents may occur
Solution Approach 1:
The patent precisely controls the concentration parameter of metal atoms within the range of 1×10^19 to 1×10^21 atoms/cm³. This optimized parameter range achieves the desired reduction in threshold voltage and increase in mobility while preventing excessive metal atom accumulation that would cause leakage currents, thus resolving the contradiction between improved mobility and harmful leakage effects
3Reliability
If high concentration of metal atoms is used to lower threshold voltage, then mobility improves, but crystal grain size control becomes difficult
Solution Approach 1:
The patent optimizes the metal atom concentration parameter to a specific range (1×10^19 to 1×10^21 atoms/cm³) that enables proper crystallization at lower temperatures. This parameter optimization ensures that crystal grains grow to appropriate sizes (0.5 μm to 5 μm) while maintaining high mobility, resolving the contradiction between improved mobility and precise crystal grain size control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the mobility of the channel semiconductor layer and lowers the threshold voltage of memory cells, preventing leakage currents while maintaining optimal crystal grain size and insulating film integrity.
Implementation Method 1
metal atoms, such as nickel, into a channel semiconductor layer, which are deposited on a surface of the channel semiconductor layer
Implementation Method 2
diffused in to crystallize the layer at a lower temperature
Implementation Method 3
diffused in to crystallize the layer at a lower temperature, increasing the particle diameter of crystal grains in the channel semiconductor layer
Data Source
AI summary
A semiconductor device includes a semiconductor layer containing metal atoms, a charge storage layer provided on a surface of the semiconductor layer via a first insulating film, and an electrode layer provided on a surface of the charge storage layer via a second insulating film. The thickness of the first insulating film is 5 nm or more and 10 nm or less. The concentration of the metal atoms in the semiconductor layer is 5.0×1017 [EA/cm3] or higher and 1.3×1020 [EA/cm3] or lower.


