Channel-Less IC Layout Wiring for Shorter Interconnects
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Solution Overview
Problem
Conventional integrated circuit (IC) chip designs require numerous channels for interconnection lines and buses, leading to increased chip size, signal delays, and inefficiencies due to longer wire lengths and the need for additional clock buffer circuits.
Innovation Solution
The proposed solution involves routing interconnection lines directly between partitions without the use of pre-established channels, utilizing transistors within the partitions to provide buffer circuits and reinforce signal strength, thereby reducing the need for dedicated channel space and minimizing signal degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If channels are provided for routing interconnection lines between partitions, then signal integrity is maintained, but chip area increases and interconnection length increases
Solution Approach 1:
The patent extracts the buffer circuit functionality from dedicated channel regions and relocates it to partition regions. This allows interconnection lines to be routed directly through partitions without requiring separate channel spaces, thereby reducing chip area while maintaining signal integrity through the relocated buffer circuits.
Solution Approach 2:
The patent makes partition regions serve dual functions: housing functional circuitry and providing routing paths for interconnection lines. This eliminates the need for separate channel regions, as partitions become multi-functional areas that both process signals and transmit them between components.
2Reliability
If channels are provided for routing interconnection lines between partitions, then signal integrity is maintained, but interconnection line length increases causing delays
Solution Approach 1:
The patent extracts buffer circuits from channel regions and places them within partitions at strategic locations along interconnection paths. This enables direct routing through partitions, shortening interconnection line length while maintaining signal integrity through the relocated buffers that refresh signals at optimal points.
3Adaptability or versatility
If numerous channels are provided for interconnection lines, then connectivity between components is ensured, but device complexity increases
Solution Approach 1:
The patent makes partition regions serve dual functions as both functional circuitry housings and routing channels. This eliminates the need for separate channel structures, reducing device complexity while maintaining full connectivity between partitions through the unified partition regions that provide both processing and transmission capabilities.
4Reliability
If buffer circuits are provided in channel regions, then signal strength is maintained, but chip area increases
Solution Approach 1:
The patent extracts buffer circuits from dedicated channel regions and relocates them to partition regions where they can share space with functional circuitry. This relocation maintains signal strength through properly positioned buffers while reducing chip area by eliminating separate channel spaces and consolidating buffer circuits into existing partition areas.
Data Source
AI summary
An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.