Channel-Mapped Flash Translation Layers for Large-Capacity Storage

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Solution Overview

Problem

The increase in size of the logical to physical (L2P) table entries in non-volatile memory devices, such as NAND flash memory, leads to issues like reduced cache utilization, increased write amplification, reduced write performance, and shorter device life due to unaligned entries and inefficient programming models.

Innovation Solution

Divide the logical address space into segments and map these segments to different channels, using a breadth-first programming approach to ensure L2P entries remain Dword-aligned, allowing for parallel data operations across multiple channels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the size of L2P table entries is increased to accommodate larger storage capacity, then the storage capacity is improved, but cache utilization is reduced and write performance deteriorates

Engineering Contradiction:
Improvestorage capacityVSAvoidwrite performance
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent segments the L2P table into multiple smaller tables distributed across different memory channels. Each channel maintains its own L2P table, which keeps the table size manageable and fits within cache memory constraints. This segmentation allows the system to support large storage capacity while maintaining efficient cache utilization and write performance on each individual channel.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If the size of L2P table entries is increased to accommodate larger storage capacity, then the storage capacity is improved, but write amplification is increased

Engineering Contradiction:
Improvestorage capacityVSAvoidwrite amplification
Core Design Contradiction:
Quantity of substanceVSLoss of energy

Solution Approach 1:

By dividing the L2P table across multiple channels, each channel handles a subset of mapping operations. This reduces the write amplification effect on each individual channel, as updates are distributed rather than concentrated in a single large table. The segmentation strategy maintains lower write amplification ratios while supporting large storage capacity.

Inventive Principle:
Principle #1Segmentation

3Quantity of substance

If L2P table entries are made larger to support more addresses, then the storage capacity is improved, but device life is reduced

Engineering Contradiction:
Improvestorage capacityVSAvoiddevice life
Core Design Contradiction:
Quantity of substanceVSDuration of action of stationary object

Solution Approach 1:

The patent distributes L2P table entries across multiple channels, reducing the write load on each channel. This segmentation approach decreases the cumulative write amplification and stress on individual memory cells, thereby extending the overall device life while maintaining support for large storage capacity.

Inventive Principle:
Principle #1Segmentation

4Device complexity

If a single large L2P table is used to map all logical block addresses, then the device complexity is reduced, but cache utilization is reduced

Engineering Contradiction:
Improvemapping structureVSAvoidcache utilization
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent segments the single large L2P table into multiple smaller channel-specific L2P tables. This segmentation improves cache utilization by keeping individual table sizes within cache memory limits, while the overall mapping structure remains relatively simple through the use of channel identifiers and distributed table architecture.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250291718A1Segmentation of a flash translation layer of a non-volatile memory device with large storage capacity
Publication Date: 2025.09.18 MICROCHIP TECHNOLOGY INC
  • US20250291718A1 patent drawing
  • US20250291718A1 patent drawing
  • US20250291718A1 patent drawing

AI summary

A controller may map different ranges of logical block addresses, of a flash translation layer of a storage device, to different segments; and map the different segments to different channels of the storage device. The controller may receive a command to perform a write operation on the storage device. The command may identify a range of logical block addresses. The controller may identify a segment, of the different segments, mapped to the range of logical block addresses; and perform the write operation using one or more channels, of the different channels, mapped to the identified segment.