Semiconductor Channel Patterning with Dual CMP for Mobility
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Solution Overview
Problem
As semiconductor devices are scaled down, they face challenges such as the short channel effect and deteriorated operation characteristics, particularly in achieving high performance field effect transistors with improved carrier mobility.
Innovation Solution
A patterning method involving the sequential formation of buffer layers and channel semiconductor layers with specific lattice constants, followed by chemical mechanical polishing (CMP) processes using distinct slurries to planarize and pattern the layers, thereby enhancing charge mobility properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor devices are scaled down to improve integration density, then device size decreases, but short channel effect and deteriorated operation characteristics occur
Solution Approach 1:
The patent changes the material composition parameter of the channel semiconductor layer, transitioning from pure silicon to silicon-germanium alloy with varying germanium concentrations. This parameter change modifies the material's physical properties including carrier mobility and effective mass, enabling improved operation characteristics in scaled-down devices while maintaining appropriate device size
2Reliability
If carrier mobility is increased to improve transistor performance, then charge mobility improves, but manufacturing complexity increases due to multiple CMP processes
Solution Approach 1:
The patent segments the channel semiconductor layer into multiple sub-layers with different germanium concentrations (e.g., first channel layer with 5-15% Ge, second channel layer with 15-30% Ge). Each sub-layer is formed and polished separately using dedicated CMP processes, allowing optimization of carrier mobility in each region while managing manufacturing complexity through systematic process segmentation
Solution Approach 2:
Different regions of the channel semiconductor layer are assigned different germanium concentrations tailored to specific functional requirements. The lower germanium concentration region provides baseline mobility, while the higher germanium concentration region enhances carrier mobility in critical areas, achieving localized optimization of charge transport properties
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves the charge mobility and electric characteristics of semiconductor devices by effectively planarizing the channel semiconductor layers and reducing surface damage, leading to better reliability and performance of transistors.
Implementation Method 1
performing a first CMP process to remove at least a portion of the first portion of the second channel semiconductor layer, removing the capping insulating layer to expose a top surface of the first channel semiconductor layer, and performing a second CMP process to remove at least a portion of a second portion of the second channel semiconductor layer protruding upwardly with respect to the top surface of the first channel semiconductor layer
Data Source
AI summary
A patterning method for fabricating a semiconductor device includes forming, for example sequentially forming, a lower buffer layer, a first channel semiconductor layer, and a capping insulating layer on a substrate, forming an opening to penetrate the capping insulating layer and the first channel semiconductor layer and expose a portion of the lower buffer layer, forming a second channel semiconductor layer to fill the opening and include a first portion protruding above the capping insulating layer, performing a first CMP process to remove at least a portion of the first portion, removing the capping insulating layer, and performing a second CMP process to remove at least a portion of a second portion of the second channel semiconductor layer protruding above the first channel semiconductor layer.