Channel Pillar Memory Structure With Self-Aligned Gate Stack

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Solution Overview

Problem

Existing semiconductor memory devices face challenges in achieving high integration density and operational reliability, particularly in three-dimensional structures, due to misalignment issues between channel pillars and the need for multi-layered drain selection transistors.

Innovation Solution

The semiconductor memory device incorporates a gate stack with single-layered conductive patterns and a second channel pillar connected to a first channel pillar through a gate insulation layer, eliminating the need for dummy structures and enhancing alignment, thereby improving integration and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If multi-layered drain selection transistors are used to increase driving capacity, then the driving capacity is improved, but the device complexity and chip size increase

Engineering Contradiction:

Improvedriving capacityVSAvoidtransistor structure

Core Design Contradiction:

PowerVSDevice complexity

Solution Approach 1:

The patent merges the drain selection transistor and memory cell transistor into a single integrated structure. The gate stack serves dual purposes: as the drain selection transistor gate and as the memory cell transistor gate. This integration eliminates the need for separate multi-layered transistor structures while maintaining driving capacity through the shared gate control mechanism.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The gate stack is designed to perform multiple functions simultaneously. It acts as both the drain selection transistor gate and the memory cell transistor gate, providing universal control for both transistor types. This multi-functionality reduces the overall number of components needed while maintaining the required driving capacity for drain selection operations.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If channel pillars are precisely aligned to improve reliability, then operational reliability is improved, but manufacturing precision requirements increase

Engineering Contradiction:

Improveoperational reliabilityVSAvoidalignment precision

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The gate stack is formed first as a reference structure before the channel pillars are created. This preliminary formation of the gate stack provides a stable alignment reference that guides subsequent channel pillar fabrication. By establishing the gate stack position beforehand, the manufacturing process achieves precise alignment without requiring extremely tight tolerances in later steps.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The gate stack serves as an intermediary structure that mediates the alignment between different channel pillars. Rather than directly aligning channel pillars to each other with high precision requirements, the gate stack acts as a common reference plane that simplifies the alignment process and reduces the cumulative precision requirements.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Measurement precision

If dummy structures are added to ensure proper alignment, then alignment accuracy is improved, but the device complexity and chip area increase

Engineering Contradiction:

Improvealignment accuracyVSAvoidchip area

Core Design Contradiction:

Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent removes the need for dummy structures by integrating the alignment function directly into the gate stack and channel pillar formation process. Instead of adding extra dummy elements to facilitate alignment, the design extracts the alignment requirement into the essential functional structures themselves, eliminating unnecessary components and reducing chip area.

Inventive Principle:

Principle #2Taking out (Extraction)

4Area of stationary object

If integration density is increased to reduce chip size, then chip area is reduced, but manufacturing complexity and alignment difficulty increase

Engineering Contradiction:

Improvechip areaVSAvoidthree-dimensional structure

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent transitions from a planar two-dimensional layout to a three-dimensional vertical structure with stacked gate electrodes and channel pillars extending in the vertical direction. This dimensional change allows higher integration density by utilizing the vertical space above the substrate, effectively packing more functional elements into a smaller horizontal footprint while maintaining manufacturability through standard vertical fabrication processes.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12526987B2Method of fabricating the semiconductor memory device including channel pillar

Publication Date: 2026.01.13 SK HYNIX INC

AI summary

Provided is a method of fabricating the semiconductor memory device. A stack layer, which includes sacrificial layers and first insulating interlayers alternately stacked, is formed. The sacrificial layers are positioned at an uppermost layer of the stack layer. A plurality of channel holes are formed through the stack layer. A first channel pillar is formed in each of the channel holes. A mold layer is formed on the stack layer with the first channel pillar. The mold layer includes a mold hole configured to partially expose the first channel pillar. A second channel pillar is formed in the mold hole. The mold layer and the sacrificial layer at the uppermost layer of the stack layer are then removed.