Channel Pillar Junction Layout for Dense Semiconductor Memory
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing integration density while maintaining operational reliability, particularly in reducing chip size and preventing characteristic deterioration due to misalignment of channel pillars.
Innovation Solution
The semiconductor memory device incorporates a second channel pillar as the channel of the drain selection transistor, eliminating the need for dummy channel structures and using a single-layered conductive pattern structure, which improves driving capacity and reduces chip size, and employs a mold layer to align the first and second channel pillars effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy channel structures are used to maintain alignment, then manufacturing precision is improved, but device complexity and chip size increase
Solution Approach 1:
The invention removes the dummy channel structure from the device architecture. Instead of adding extra alignment structures, the patent uses the gate stack itself as the alignment reference for forming channel holes, eliminating unnecessary components while maintaining manufacturing precision
Solution Approach 2:
The gate stack serves multiple functions: it acts as both the functional gate structure and the alignment reference for channel hole formation. This multi-functionality eliminates the need for separate dummy structures, reducing device complexity while maintaining precision
2Power
If multiple layered conductive patterns are used, then driving capacity is improved, but manufacturing complexity and chip size increase
Solution Approach 1:
The invention merges the drain selection line and source selection line into a single conductive pattern layer. This consolidation maintains the necessary electrical functionality and driving capacity while significantly reducing manufacturing complexity and chip size compared to separate layered structures
3Quantity of substance
If channel pillars are formed through all conductive patterns including uppermost pattern, then integration density is improved, but characteristic deterioration occurs due to misalignment
Solution Approach 1:
The invention introduces the gate stack as an intermediary alignment reference between the channel hole formation process and the conductive patterns. By using the gate stack's physical structure as the positioning基准, the patent prevents misalignment issues while achieving high integration density
Solution Approach 2:
The gate stack is formed first before channel holes are etched. This preliminary action establishes a fixed alignment reference that guides subsequent channel hole formation, ensuring proper positioning through all conductive patterns without misalignment deterioration
Data Source
AI summary
Provided is a semiconductor memory device and method of fabricating the semiconductor memory device. A semiconductor memory device includes a gate stack and a plurality of channel structures. The gate stack includes a plurality of stacked conductive patterns spaced apart from each other. The plurality of the channel structures is formed through the gate stack. Each of the channel structures includes a first channel pillar, a second channel pillar and a gate insulation layer. The first channel pillar is formed through the conductive patterns except for an uppermost conductive pattern. The second channel pillar is formed through the uppermost conductive pattern. The second channel pillar is configured to make contact with the first channel pillar. The gate insulation layer is interposed between the uppermost conductive pattern and the first and second channel pillars.