Asymmetric Channel Roughness for DRAM Word Line Short Prevention
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Solution Overview
Problem
The challenge in DRAM device manufacturing lies in shrinking memory cell area due to word line spacing errors during lithography, leading to channel shorting issues and overlay errors, which affect the performance and yield of semiconductor devices.
Innovation Solution
A semiconductor device structure with a channel layer having different roughness on its sidewalls, allowing for flexible adjustment of the channel and gate dielectric thickness, and eliminating the need for a lithography process to form openings for the gate dielectric structure and channel layer between separated word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the memory cell area is shrunk by reducing word line spacing, then the integration density is improved, but the risk of electrical shorts between the channel and word line increases due to overlay errors
Solution Approach 1:
The channel layer is designed with asymmetric roughness characteristics: one sidewall has a first roughness while the opposite sidewall has a second roughness different from the first. This asymmetric structure creates different effective widths at different sides of the channel, allowing the channel to be positioned farther from the word line on the side prone to overlay errors, thereby preventing electrical shorts while maintaining small memory cell area
Solution Approach 2:
Different portions of the channel layer are given different roughness properties tailored to their specific functional requirements. The sidewall adjacent to the word line has modified roughness to prevent shorts, while the opposite sidewall has different roughness to maintain electrical performance. This local differentiation resolves the contradiction between small area and short prevention
2Ease of manufacture
If a lithography process is used to form openings for the gate dielectric structure and channel layer, then the manufacturing process is established, but overlay errors cause misalignment and potential shorts
Solution Approach 1:
The channel layer structure itself provides the alignment reference and positioning function. By forming the channel layer with asymmetric roughness directly on the word line structure, the channel layer becomes self-aligned to the word line, eliminating the need for separate lithography alignment steps that cause overlay errors. The structure serves its own alignment function
Solution Approach 2:
The asymmetric roughness pattern is established in the channel layer formation step before the gate dielectric structure is formed. This preliminary establishment of the asymmetric structure ensures that subsequent layers are built on a pre-positioned, self-aligned foundation, preventing misalignment issues that would arise from later lithography steps
3Device complexity
If the channel layer has uniform thickness, then the manufacturing process is simple, but the performance and yield are reduced due to inability to compensate for overlay variations
Solution Approach 1:
The channel layer is designed with non-uniform roughness distributed across different sidewalls. This local variation in surface morphology allows different regions of the channel to have different effective electrical characteristics, compensating for overlay variations and improving device yield while maintaining manufacturing feasibility
Data Source
AI summary
A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a first word line, a second word line, a gate dielectric structure, a channel layer, and a bit line. The first word line and second word line extend along a first direction. The gate dielectric structure is disposed on a first sidewall of the first word line and on a second sidewall of the second word line. The channel layer is disposed on a first sidewall of the gate dielectric structure. The bit line is disposed on the channel layer and extends along a second direction substantially perpendicular to the first direction. A first roughness of a first sidewall of the channel is different from a second roughness of a second sidewall of the channel layer.