Channel Routing for Memory Devices via Redistribution Layers
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Solution Overview
Problem
Existing memory devices face challenges in achieving high reliability, low latency, and low power consumption while being scalable and cost-effective, particularly due to long conductive paths that require increased power for operations and compatibility issues with preexisting interfaces.
Innovation Solution
The implementation of channel routing systems that distribute channel terminals throughout the die area to shorten conductive paths and use redistribution layers with interconnects to couple memory devices with host interfaces, facilitating communication between memory devices and host devices even with mismatched bumpouts, such as HBM or HBM2 interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If channel terminals are centralized in memory devices, then interface compatibility is improved, but conductive path length increases leading to higher power consumption
Solution Approach 1:
The patent segments the centralized interface into multiple distributed channel terminals across the die area. Each channel terminal serves a local region, breaking down the single centralized interface into multiple smaller interfaces that are spatially distributed to reduce conductive path lengths.
Solution Approach 2:
The patent transitions from a two-dimensional centralized interface layout to a three-dimensional distributed architecture where channel terminals are positioned at multiple locations across the die, utilizing vertical stacking and lateral distribution to create shorter conductive paths in multiple spatial dimensions.
2Use of energy by moving object
If channel terminals are distributed throughout the die area, then conductive path length is reduced lowering power consumption, but interface compatibility with preexisting interfaces deteriorates
Solution Approach 1:
The patent introduces redistribution layers as intermediary structures between the distributed channel terminals and external interfaces. These redistribution layers act as mediators that collect signals from multiple distributed terminals and present them in standardized formats compatible with preexisting interfaces like HBM or HBM2.
Solution Approach 2:
The redistribution layers are designed with multi-functionality, serving both to aggregate signals from distributed channel terminals and to provide standardized interface compatibility with various external memory interfaces, making the distributed architecture universally compatible.
3Ease of manufacture
If centralized interfaces are used, then manufacturing simplicity is maintained, but latency increases due to long conductive paths
Solution Approach 1:
The patent segments the monolithic centralized interface into multiple smaller channel terminal units distributed across the die. This segmentation allows each unit to be manufactured using standard processes while the overall distributed architecture achieves lower latency through shorter local conductive paths.
Solution Approach 2:
The patent applies local quality by optimizing each distributed channel terminal unit for its specific location on the die, allowing local conductive paths to be minimized while maintaining overall manufacturing simplicity through standardized unit designs that can be replicated across different locations.
4Loss of time
If distributed channel terminals are implemented, then latency is reduced through shorter conductive paths, but device complexity increases
Solution Approach 1:
The patent segments the memory device into multiple independent channel terminal units, each handling local I/O operations. This segmentation reduces latency by localizing access paths while managing complexity through modular design where each segment follows standardized patterns.
Solution Approach 2:
The patent merges multiple distributed channel terminal units through redistribution layers that combine their individual conductive paths into unified interface connections. This merging approach manages the inherent complexity of distributed architecture by systematically consolidating paths at strategic points in the signal flow.
Data Source
AI summary
Systems and devices for routing signals between a memory device and an interface of a host device are described. Some memory technologies may have a defined, preconfigured interface (e.g., bumpout), where each interface terminal may have a specific location and a specific function. Using preconfigured interfaces may allow device maker and memory makers to make parts that are able to connect with one another without special designs. In some cases, a memory device may include a redistribution layer that includes a plurality of interconnects that may be configured couple channel terminals of the memory device with an interface associated with the host device.