Channel Stack Separation With Dielectric Wall for MOSFET Leakage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor manufacturing, as the characteristic dimension of integrated circuits decreases, the channel length of MOSFETs becomes smaller, leading to a deterioration in gate structure control, increased subthreshold leakage, and difficulty in pinching off the channel, known as the short-channel effect (SCE), which affects the electrical performance of semiconductor devices.
Innovation Solution
A method for forming a semiconductor structure involves creating a discrete combined pattern with a mandrel and spacer layer on the initial channel stack, forming a dielectric wall, and using the spacer layer as a mask to etch the channel stack, resulting in a separate channel stack with improved morphology uniformity and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the channel length of MOSFET is reduced to adapt to smaller characteristic dimensions, then the device size is reduced, but the gate structure control capability deteriorates and subthreshold leakage increases
Solution Approach 1:
The patent transitions from planar transistor architecture to three-dimensional transistor structures (FinFET and gate-all-around). By adding vertical dimensions through fin structures and surrounding gates, the gate control capability is enhanced without increasing the horizontal channel length, thus maintaining small device footprint while improving gate control over the channel
Solution Approach 2:
The gate structure completely surrounds the channel in gate-all-around transistors, with the gate wrapping around the channel from all directions. This nested configuration maximizes the gate's control capability over the channel while maintaining a compact device structure suitable for small characteristic dimensions
2Reliability
If a dielectric wall is formed at the boundary between device regions, then bridging between source/drain doped layers is prevented, but the manufacturing process complexity increases
Solution Approach 1:
The discrete combined pattern (mandrel and spacer) is formed in advance at the boundary between device regions before the source/drain doped layers are deposited. This preliminary structure serves as a template for subsequent dielectric wall formation, ensuring proper positioning and preventing bridging between adjacent doped regions
Solution Approach 2:
The discrete combined pattern consisting of mandrel and spacer layers acts as an intermediary structure during manufacturing. It serves as a temporary template that guides the formation of the dielectric wall, enabling precise positioning without requiring complex direct patterning of the dielectric material itself
3Manufacturing precision
If the initial channel stack is etched using the spacer layer as a mask, then the separate channel stack has good morphology uniformity, but the mandrel layer must be removed adding process steps
Solution Approach 1:
The spacer layer, which is already present on the mandrel structure, serves dual purposes: it maintains the uniform morphology of the channel stack during etching and simultaneously acts as the etch mask. The existing spacer structure eliminates the need for separate mask formation steps, reducing overall process complexity while maintaining manufacturing precision
Data Source
AI summary
A semiconductor structure and a method for forming the same are provided. One form of a method for forming a semiconductor structure includes: providing a base, the base including a first device region and a second device region, the base including an initial substrate and one or more initial channel stacks located on the initial substrate, and the initial channel stack including a sacrificial material layer and a channel material layer located on the sacrificial material layer; forming a discrete combined pattern on the initial channel stack, the combined pattern including a mandrel layer and a spacer layer located on a side wall of the mandrel layer, and the combined pattern exposing a boundary between the first device region and the second device region; forming a dielectric wall running through the initial channel stack at the boundary between the first device region and the second device region; and removing the mandrel layer. In embodiments and implementations of the present disclosure, the spacer layer has good uniformity, and the initial channel stack is etched by using the spacer layer as a mask to form a separate channel stack which has good morphology uniformity, which is conducive to improving the uniformity of the semiconductor structure performance.