Transistor Channel Stress Transfer via Sacrificial Annealed Layer
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Solution Overview
Problem
Conventional methods for imparting stress in semiconductor transistor channel regions often require altering the composition of doped regions, leading to compromised device performance, and involve selecting high-stress conductive materials that may not meet all requirements, such as conductivity and hermeticity.
Innovation Solution
The method involves depositing a sacrificial stressed material on adjacent layers to the semiconductor material with incorporated dopants, followed by a rapid thermal anneal to retain stress in these layers, which is then imparted to the channel region without altering the doped region compositions or permanently depositing high-stress conductive materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If conventional methods are used to impart stress in channel regions, then stress is incorporated, but the composition of doped regions must be altered which compromises device performance
Solution Approach 1:
The patent separates the stress imparting function from the doped regions by introducing an intermediate layer. The stressed material is deposited on the intermediate layer, which then transfers stress to the channel region without requiring composition changes in the source and drain regions. This segmentation allows stress incorporation while preserving doped region integrity and device performance.
Solution Approach 2:
The patent introduces an intermediate layer as a mediator between the stressed material and the semiconductor substrate. This intermediate layer receives the stressed material deposition, undergoes rapid thermal annealing to retain stress, and then transfers the stress to the channel region. The intermediary enables stress transfer without direct contact between the stressed material and doped regions, avoiding composition alterations.
2Stress or pressure
If high-stress conductive materials are selected to impart stress, then stress level increases, but conductivity and hermeticity requirements may not be met
Solution Approach 1:
The patent divides the system into functionally separate components: the stressed material provides stress, the intermediate layer provides structural support and stress transfer, and the conductive material (if used) provides electrical functionality. This segmentation allows each material to be optimized for its specific function, enabling selection of high-stress materials without compromising conductivity or hermeticity requirements.
Solution Approach 2:
The patent changes the selection criterion for the stressed material from requiring simultaneous optimization of stress, conductivity, and hermeticity to only requiring high stress capability. The rapid thermal annealing process parameter (heating rate greater than 200°C/second) is introduced to enable stress retention in the intermediate layer, expanding material selection flexibility for the stressed material.
3Stress or pressure
If rapid thermal annealing is performed at heating rate greater than 200°C/second, then stress is retained in adjacent layers, but process complexity increases
Solution Approach 1:
The patent utilizes the phase transition behavior of materials during rapid thermal annealing. The extremely fast heating rate (greater than 200°C/second) causes the intermediate layer to undergo thermal excitation that allows it to retain stress from the deposited stressed material. This phase transition approach enables stress retention without requiring complex process sequences, as the stress transfer occurs naturally during the annealing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for desired stress levels in the channel region without changing the composition of source and drain regions, improving transistor performance by increasing charge carrier mobility and drive current while expanding the selection of materials based on stress imparting ability rather than other characteristics.
Implementation Method 1
heating the stressed material and the adjacent layer. In some embodiments, the heating may be done with a rapid thermal process that raises the temperature of the material to several hundred degrees Celsius in less than or about one second. Embodiments of these rapid thermal processes include a spike anneal that heats the stressed material and adjacent layer at a heating rate greater than or about 200° C.
Implementation Method 2
The adjacent layer may be characterized by increased stress after the deposition of the stressed material. As a result of the heating, the adjacent layer retains at least a portion of the increased stress after the removal of the stressed material.
Data Source
AI summary
Examples of the present technology include processing methods to incorporate stress in a channel region of a semiconductor transistor. The methods may include depositing a stressed material on an adjacent layer, where the adjacent layer is disposed between the stressed material and semiconductor material having an incorporated dopant. The adjacent layer may be characterized by an increased stress level after the deposition of the stressed material. The method may further include heating the stressed material and the adjacent layer, and removing the stressed material from the adjacent layer. The adjacent layer retains at least a portion of the increased stress after the removal of the stressed material. Examples of the present technology also include semiconductor structures having a conductive layer with first stress, and an intermediate layer with second stress in contact with the conductive layer. The second tensile stress may be at least ten times the first tensile stress.