Channel Subsystem Data Router for Direct Host Memory Access
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Solution Overview
Problem
Existing input/output processing systems require data to be stored in local channel memory for error checking, leading to increased response times and reduced I/O start rates due to the need for store and forward operations between the host computer and host bus adaptor (HBA).
Innovation Solution
A data router is introduced in the channel subsystem that allows the HBA to directly access host memory by generating and using address control structures, enabling direct data transfer and error checking without storing data in local channel memory, thereby improving I/O start rates and reducing response times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is stored in local channel memory for error checking, then reliability is improved, but response time increases and I/O start rates decrease
Solution Approach 1:
The patent extracts the error checking function from the local channel memory store-and-forward process. Instead of storing data in local channel memory and then forwarding it, the system directly transfers data from host memory to the HBA while performing error checking during the transfer process itself, eliminating the intermediate storage step that causes delay
Solution Approach 2:
The patent implements preliminary error checking validation before data is fully transferred. The channel subsystem validates error checking information in advance during the transfer process, allowing the HBA to receive verified data without waiting for post-transfer error checking, thus reducing response time while maintaining reliability
2Reliability
If data is stored in local channel memory for error checking, then reliability is improved, but I/O start rates are reduced
Solution Approach 1:
The patent removes the intermediate local channel memory storage step from the data transfer path. Data flows directly from host memory to HBA with error checking performed during transfer, eliminating the store-and-forward bottleneck that limits I/O start rates while preserving error checking capability through direct validation of transfer operations
Solution Approach 2:
The channel subsystem performs preliminary setup of error checking parameters and validation rules before data transfer begins. This preliminary configuration allows the HBA to perform error checking in parallel with data transfer rather than sequentially, increasing I/O start rates while maintaining reliability
3Productivity
If direct access to host memory is implemented, then I/O start rates increase and response times decrease, but system complexity increases
Solution Approach 1:
The patent introduces address control structures as intermediary data structures that manage the complexity of direct host memory access. These structures contain pre-calculated addressing information that simplifies the HBA's access to host memory, allowing direct access performance while managing system complexity through structured address management
Solution Approach 2:
The channel subsystem performs preliminary calculation and preparation of address control structures before data transfer. This preliminary addressing setup eliminates the need for complex real-time address calculation during data transfer, enabling direct host memory access with improved I/O start rates while containing system complexity in the pre-processing phase
Data Source
AI summary
On embodiment includes a computer program product for performing a method including: obtaining information relating to an I/O operation at a channel subsystem in a host computer system; generating addressing information and forwarding the addressing information from at least one channel to a network interface between the channel subsystem and at least one I/O device, the addressing information specifying a location in a local channel memory; forwarding an I/O command message to the at least one I/O device via the network interface; responsive to the I/O command message, receiving a data transfer request from the network interface that includes the addressing information; responsive to receiving the data transfer request, accessing one of a plurality of address control words (ACWs), each ACW specifying an address of a location in a host computer memory; and routing the data transfer request to the host memory location specified in the ACW.