Channel Via Layout for High-Density Contacts Across Cavities
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Solution Overview
Problem
Existing semiconductor devices face limitations in the number and density of vias due to the presence of channels, cavities, or voids, which restrict the routing of signals and the density of through substrate vias (TSVs).
Innovation Solution
The implementation of channel vias extending to the bottom surface of channels within semiconductor devices, allowing for a higher density of vias by using smaller diameters and arranging them in arrays along the channel bottom, with conductive lines connecting these vias to pads on the channel ridges, and encapsulating layers to prevent contact with fluids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional ridge vias are used in semiconductor devices with channels, then the structure is simpler to manufacture, but the via density is limited due to the channel obstruction
Solution Approach 1:
The patent transitions from traditional ridge vias that route signals along the top surface of channels to channel vias that extend to the bottom surface of channels, utilizing the vertical dimension to achieve higher via density. This dimensional change allows vias to be positioned at the channel bottom where more routing space is available, thereby increasing the quantity of vias without proportionally increasing structural complexity.
Solution Approach 2:
Instead of routing vias from the top surface along the ridge (conventional approach), the patent inverts the routing approach by extending vias to the bottom surface of the channel and connecting them to pads on the ridge from below. This inversion enables higher via density by utilizing the previously underutilized bottom surface area.
2Quantity of substance
If vias are extended to the bottom surface of channels, then via density increases, but the risk of fluid contact and corrosion increases
Solution Approach 1:
The patent introduces an encapsulating layer as an intermediary barrier between the channel vias and the fluid within the channel. This encapsulation layer prevents direct contact between the via structures and the fluid, thereby eliminating the corrosion risk while maintaining the high via density achieved through bottom-surface routing.
3Quantity of substance
If channel vias with smaller diameters are used to increase density, then via density improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes parameter changes in the via formation process, specifically transitioning to smaller via diameters to increase density. By carefully controlling the via diameter parameter and optimizing the manufacturing process accordingly, the patent achieves higher via density while managing the increased precision requirements through process optimization rather than fundamental manufacturing changes.
Data Source
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Figure 3A~3B
AI summary
Novel tools and techniques are provided for implementing a semiconductor package or a chip package, and more particularly methods, systems, and apparatuses are provided for implementing a semiconductor package or a chip package including a one or more channel vias. In various embodiments, an apparatus includes a first layer comprising a channel; a first via extending though the first layer to a first surface of the channel; and a line connecting the first via to a pad. In some cases, the first surface is located at a bottom of the channel.