Chaotic CMOS Circuit for NP-Hard Optimization via Self-Organized Criticality

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Solution Overview

Problem

Conventional computers are inefficient in solving large problems with many interacting variables, as they are NP-hard and sequential in nature, making it difficult to handle complex tasks such as image recognition and optimization of large systems.

Innovation Solution

A chaotic circuit with a matrix of oscillator unit cells interconnected by transmission gates is used, capable of generating random bits by controlling bifurcation parameters to drive the circuit from the Markovian dynamics regime into the chaotic dynamics regime, allowing for self-organized criticality and efficient information processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional computers are used to solve large problems with many interacting variables, then sequential arithmetic operations can be performed, but the computational effort becomes NP-hard and efficiency deteriorates

Engineering Contradiction:
Improvecomputational efficiencyVSAvoidproblem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent replaces conventional sequential mechanical computation with a physical chaotic system that naturally evolves to solve optimization problems. The chaotic circuit's inherent dynamics substitute for step-by-step algorithmic processing, enabling parallel exploration of solution spaces and avoiding NP-hard computational bottlenecks.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the fundamental parameter of computation from sequential digital operations to continuous physical dynamics. By tuning bifurcation parameters of the chaotic system, the computation transitions between different regimes (Markovian to chaotic), enabling efficient solution of complex problems that are intractable for conventional computers.

Inventive Principle:
Principle #35Parameter changes

2Ease of operation

If the von Neumann architecture is used for data processing, then centralized calculation can be performed, but data movement in and out of the CPU creates inefficiency for large interactive problems

Engineering Contradiction:
Improvedata processing capabilityVSAvoiddata movement time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The chaotic circuit performs computation intrinsically through its natural dynamics without requiring external data movement or centralized control. The system self-organizes to find solutions, eliminating the need for data to be moved in and out of a central processor and reducing communication overhead.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent divides the computational task into distributed interactions among multiple units in the chaotic system. Each unit contributes to the overall solution through local interactions, replacing the centralized von Neumann architecture with a distributed parallel system that processes information simultaneously across all units.

Inventive Principle:
Principle #1Segmentation

3Measurement precision

If exact analytical solutions are sought for complex problems, then precise answers can be obtained, but the computational effort required becomes prohibitive for NP-hard problems

Engineering Contradiction:
Improvesolution accuracyVSAvoidcomputational time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent exploits phase transitions in chaotic systems, specifically the transition from Markovian to chaotic regimes through bifurcation parameter changes. This phase transition enables the system to efficiently explore the solution space and converge to accurate solutions without requiring exhaustive computational effort, providing a shortcut for NP-hard problems.

Inventive Principle:
Principle #36Phase transitions

Data Source

PatentUS10147045B2Self-organized critical CMOS circuits and methods for computation and information processing
Publication Date: 2018.12.04 RGT UNIV OF CALIFORNIA
  • US10147045B2 patent drawing
  • US10147045B2 patent drawing
  • US10147045B2 patent drawing

AI summary

A circuit that makes use of chaos or self-organized criticality to generate a matrix of bits for computation and information processing. The example embodiment utilizes CMOS circuitry and can solve optimization problems. A plurality of unit cells includes multiple transistors in a lattice formation that set voltages as state variables to other transistor cells. Adjustable bifurcation parameters are utilized to bring the chaotic circuit in and out of the chaotic regime. A processing unit with software are utilized for implanting a problem of interest into the chaotic circuit, while data latches or analog to digital converters provide for reading out the voltages from the chaotic circuit.