Rounding Charge Accumulation Layer Corners to Suppress Leakage Current
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Solution Overview
Problem
Nonvolatile semiconductor memory devices with stacked gate structures face issues with leakage current and electrical reliability due to surface roughness and electric field concentration at the corners of the floating gate, leading to reduced capacitance and dielectric breakdown strength.
Innovation Solution
The solution involves forming a non-volatile semiconductor memory device with a specific ratio of radius of curvature (r) to equivalent oxide thickness (d) of the second gate insulating film, where r/d is not smaller than 0.5, and using a manufacturing method that includes forming a first gate insulating film, a charge accumulation layer, and a control electrode, with a buried insulating film and a second gate insulating film to round the corners of the charge accumulation layer and control gate structures, thereby reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the film thickness of the inter-electrode insulating film is increased to suppress leakage current, then leakage current is reduced, but the capacitance of the insulating film is lowered
Solution Approach 1:
The patent transitions from a planar floating gate to a three-dimensionally protruded structure, increasing the surface area in the vertical dimension. This allows maintaining lower insulating film thickness (higher capacitance) while achieving sufficient total capacitance through increased surface area, thereby suppressing leakage current without sacrificing capacitance.
Solution Approach 2:
The patent applies corner rounding to the floating gate structure, replacing sharp corners with curved surfaces. This eliminates electric field concentration at corners, reducing leakage current paths while maintaining the overall three-dimensional protruded shape for sufficient capacitance.
2Quantity of substance
If a three-dimensional protruded structure is formed to increase capacitor area, then capacitance is increased, but electric field concentration occurs at convex portions leading to increased leakage current
Solution Approach 1:
The patent applies corner rounding to the three-dimensionally protruded floating gate structure, replacing sharp convex corners with curved surfaces. This eliminates electric field concentration at corner portions while preserving the overall three-dimensional shape and its increased capacitance. The rounded corners remove the sharp edges that would otherwise serve as primary leakage current paths.
3Ease of manufacture
If polysilicon is used for the floating gate electrode, then it is easy to manufacture, but surface roughness occurs due to grain boundaries leading to electric field concentration
Solution Approach 1:
The patent applies corner rounding processing to the floating gate structure before forming the inter-electrode insulating film. This preliminary action removes surface roughness and sharp corners that would cause electric field concentration, ensuring a smooth surface for subsequent film formation and preventing leakage current issues before they can manifest in the final device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses leakage current and improves electrical reliability by reducing the electric field concentration at the corners and maintaining a favorable capacitance ratio, leading to enhanced device performance.
Implementation Method 1
an edge of the gate oxide film is damaged by the etching. Therefore, recovery due to post oxidation from the damage
Data Source
AI summary
A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.