Charge Accumulation Layer Segmentation for Virtual Ground Flash Memory
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Solution Overview
Problem
In virtual ground flash memory devices, the close proximity of charge accumulation regions leads to interference between stored charges, known as complementary bit disturb (CBD), making it difficult to scale down memory cell size without charge interference.
Innovation Solution
The solution involves forming a semiconductor device with a bit line and charge accumulation layer on a semiconductor substrate, where a word line is formed across the bit line, and a hole is etched in the charge accumulation layer between the word line and bit line, allowing for isotropic etching using phosphoric acid to create a hollow section, thereby separating adjacent charge accumulation layers and preventing charge interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the space between bit lines is reduced to accommodate miniaturization, then memory cell size is reduced, but charge accumulation regions interfere with each other causing complementary bit disturb
Solution Approach 1:
The charge accumulation layer is segmented into multiple isolated regions by removing portions of the layer. This segmentation creates separate charge accumulation regions that are electrically isolated from each other, preventing charge interference while maintaining compact memory cell dimensions.
Solution Approach 2:
Portions of the charge accumulation layer are extracted or removed to create isolation regions. By taking out specific sections of the charge accumulation layer, the patent creates physical and electrical separation between adjacent charge accumulation regions, eliminating the complementary bit disturb effect.
2Reliability
If charge accumulation regions are isolated to prevent interference, then charge interference is prevented, but memory cell size increases
Solution Approach 1:
The charge accumulation layer has different local qualities - regions where charges are accumulated and regions where the layer is removed for isolation. This local differentiation allows compact overall structure while providing sufficient isolation where needed, preventing charge interference without increasing total memory cell size.
Solution Approach 2:
The isolation is achieved in the vertical dimension by removing portions of the charge accumulation layer, rather than expanding horizontally. This dimensional approach allows charge isolation to be implemented within the existing planar footprint of the memory cell, avoiding size increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the miniaturization of memory cells without charge interference, allowing for increased integration and scaling down of memory size while maintaining data storage efficiency.
Implementation Method 1
isotropically etching the charge accumulation layer via the hole by applying phosphoric acid to the hole to form a hollow section
Implementation Method 2
applying phosphoric acid to the hole to form a hollow section
Data Source
AI summary
Devices and methods for isolating adjacent charge accumulation layers in a semiconductor device are disclosed. In one embodiment, a semiconductor device comprises a bit line formed in a semiconductor substrate, a charge accumulation layer formed on the semiconductor substrate, a word line formed on the charge accumulation layer across the bit line, and a channel region formed in the semiconductor substrate below the word line and between the bit line and its adjacent bit line. For the semiconductor device, the charge accumulation layer is formed above the channel region in a widthwise direction of the word line, and a width of the word line is set to be narrower than a distance between an end of the channel region and a central part of the channel region in a lengthwise direction of the word line.