Charge-Sensitive Amplifier Layout for Low Gate Capacitance

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Solution Overview

Problem

The existing semiconductor radiation detectors face challenges in reducing parasitic capacitance associated with wire bonding, which limits the noise performance and gain of Field Effect Transistors (FETs) used in radiation detection systems, particularly in x-ray detection systems where the stray capacitance from bond pads exceeds detector capacitance.

Innovation Solution

The integration of the gate pad of the Field Effect Transistor with the feedback capacitor forms a combined integral component, eliminating the parasitic capacitance of the gate bond pad and reducing the total capacitance at the gate, thereby improving noise performance without compromising gain.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If discrete FETs are used with wire bonding, then high gain and excellent noise performance are achieved, but parasitic capacitance from bond pads exceeds detector capacitance and limits performance

Engineering Contradiction:
Improvenoise performanceVSAvoidparasitic capacitance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The gate pad and feedback capacitor are merged into a single integral component structure. The gate pad forms one plate of the feedback capacitor, eliminating the need for separate wire bonding to the gate. This integration removes the parasitic capacitance that would otherwise be introduced by the bond pad and wire bond, while maintaining the necessary feedback capacitance for charge-sensitive amplification.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If FET input capacitance is reduced by shrinking dimensions, then noise performance improves, but FET gain is reduced

Engineering Contradiction:
Improvenoise performanceVSAvoidFET gain
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

By merging the gate pad with the feedback capacitor, the invention allows the use of smaller FET dimensions without introducing additional parasitic capacitance from separate bond pads. This enables optimization of the FET size to achieve the desired balance between noise performance and gain, as the total capacitance at the gate is now dominated by the controlled feedback capacitor rather than uncontrolled bond pad capacitance.

Inventive Principle:
Principle #5Merging (Combining)

3Object-affected harmful factors

If bond pad diameter is reduced for smaller capacitance, then parasitic capacitance decreases, but wire bonding becomes difficult

Engineering Contradiction:
Improvestray capacitanceVSAvoidwire bonding
Core Design Contradiction:
Object-affected harmful factorsVSEase of manufacture

Solution Approach 1:

The gate pad is merged with the feedback capacitor structure, eliminating the need for wire bonding to the gate entirely. The feedback capacitor is formed with one plate being the gate pad itself and the other plate being a separate electrode, with the capacitance value determined by their geometric arrangement and dielectric properties. This integration removes the wire bonding step and its associated parasitic capacitance, while the capacitor geometry can be optimized independently for minimum stray capacitance.

Inventive Principle:
Principle #5Merging (Combining)

4Object-affected harmful factors

If integrated FETs are used on the same substrate, then parasitic capacitance is reduced, but manufacturing complexity increases

Engineering Contradiction:
Improvetotal capacitanceVSAvoidintegration complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The invention integrates the feedback capacitor directly into the FET structure by forming one plate of the capacitor using the gate pad itself. This can be accomplished using standard semiconductor fabrication processes such as depositing dielectric layers and forming electrodes, without requiring complex three-dimensional integration or specialized processes. The approach achieves low total capacitance similar to fully integrated detectors while maintaining the advantages of discrete FETs and using conventional manufacturing techniques.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively reduces the total capacitance at the gate, enhancing the noise performance and resolution of radiation detectors by eliminating the parasitic capacitance of the bond pad, while maintaining the benefits of discrete FETs, similar to integrated FETs.

Implementation Method 1

an amplifier having an input connected to the drain or source of the field effect transistor and an output connected through a feedback capacitor to the gate of the field effect transistor

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS9397626B2Charge-sensitive amplifier
Publication Date: 2016.07.19 OXFORD INSTR NANOTECHNOLOGY TOOLS LTD
  • US9397626B2 patent drawing
  • US9397626B2 patent drawing
  • US9397626B2 patent drawing

AI summary

A charge-sensitive amplifier is disclosed for use in amplifying signals from a particle detector. This includes a field effect transistor having a gate, source and drain, the gate being connectable, using a gate pad, to the particle detector, for the receipt of said signals. Also included is an amplifier having an input connected to the drain or source of the field effect transistor and an output connected through a feedback capacitor to the gate of the field effect transistor. The gate pad of the field effect transistor is made to be integral with the feedback capacitor so as to reduce the capacitance of the device.