Charge Amplifier Reset Circuit for Offset Cancellation
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Solution Overview
Problem
Existing charge amplifier circuits suffer from offset errors that lead to accuracy deterioration, particularly exacerbated by reduced capacitance in the feedback branch and increased gain, posing challenges in low-power applications where fast start-up and reduced power consumption are crucial.
Innovation Solution
The proposed charge amplifier circuit incorporates a delayed reset phase and a dual feedback branch configuration with equal capacitances, allowing for efficient offset cancellation and stabilization while minimizing current consumption, thereby addressing the limitations of existing solutions in low-power contexts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the capacitance in the feedback branch is reduced to increase gain, then the amplification capability is improved, but the offset error becomes more detrimental and accuracy deteriorates
Solution Approach 1:
The patent applies preliminary action by performing offset cancellation before the main measurement operation. A dedicated reset phase is executed prior to normal operation, during which the feedback capacitor is discharged through a reset switch to eliminate offset charges. This preliminary action ensures that subsequent high-gain measurements start from a zeroed baseline, preventing offset errors from being amplified along with the signal.
Solution Approach 2:
The patent extracts the offset error component from the overall signal by isolating it during the reset phase. The reset switch specifically targets and removes only the offset charge accumulated on the feedback capacitor, separating this harmful component from the useful signal charge. This extraction allows the main amplifier to operate at high gain without amplifying the offset error.
2Measurement precision
If the gain is increased to improve sensitivity, then the detection capability is improved, but the offset error effect grows and accuracy deteriorates
Solution Approach 1:
The reset phase serves as a preliminary action that prepares the feedback capacitor by discharging any offset charges before the sensitive measurement begins. This ensures that when high gain is applied to enhance detection sensitivity, there is no offset error present to be amplified, thus maintaining output accuracy alongside improved sensitivity.
Solution Approach 2:
The reset switch acts as an intermediary element that temporarily provides a discharge path for the feedback capacitor. During the reset phase, this intermediary component allows offset charges to be removed without affecting the main signal path. Once resetting is complete, the intermediary switch opens, restoring the high-gain measurement path free from offset errors.
3Measurement precision
If a reset phase is added to cancel offset, then the accuracy is improved, but the start-up time increases
Solution Approach 1:
The patent implements periodic action by structuring the operation into distinct phases: a brief reset phase followed by the main measurement phase. The reset switch is activated periodically at the beginning of each measurement cycle to quickly discharge offset charges. This periodic resetting approach minimizes the time penalty by confining the offset cancellation to a short, scheduled interval rather than requiring continuous correction throughout the entire operation.
Solution Approach 2:
The reset phase is designed to rush through the offset cancellation process as quickly as possible. The reset switch provides a low-impedance discharge path that rapidly removes offset charges from the feedback capacitor in a short time interval. By skipping detailed gradual correction and using direct discharge, the system minimizes the time spent on offset cancellation while still achieving accurate zeroing before measurement.
Data Source
AI summary
A circuit includes an amplifier, a bias voltage node, and a first set of switches configured, based on a first reset signal having a first value, to couple first and second input nodes to the bias voltage node and to couple first and second output nodes of the amplifier. First and second feedback branches each include a respective RC network including a plurality of capacitances. The first and second feedback branches further include a second set of switches intermediate input nodes and the capacitances, and a third set of switches intermediate input nodes and the plurality of capacitances. These switches selectively couple the capacitances to the input nodes and output nodes, based on a second reset signal having a first value. The second reset signal keeps the first value for a determined time interval exceeding a time interval in which the first reset signal has the first value.