Charge Amplifier Multi-Phase Reset for Offset-Free High Gain
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Solution Overview
Problem
Existing charge amplifier circuits suffer from offset errors that deteriorate accuracy due to reduced capacitance in the feedback branch and increased gain, leading to inefficiencies in signal processing.
Innovation Solution
A multi-phase reset process involving specific switch configurations and reset signals to couple capacitors to bias voltage nodes and input/output nodes of an operational transconductance amplifier, effectively canceling offset voltage through auto-zeroing techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If capacitance in the feedback branch is reduced to increase gain, then signal amplification is improved, but offset error deteriorates accuracy
Solution Approach 1:
The patent applies preliminary action by performing offset voltage measurement and storage before the main signal amplification operation. The auto-zeroing circuit measures and stores the offset voltage in capacitors during a calibration phase, then subtracts this stored offset from the amplified signal during normal operation, thereby eliminating the detrimental effect of offset error while maintaining high gain.
Solution Approach 2:
The patent introduces an intermediary auto-zeroing circuit that includes offset measurement capacitors and switching mechanisms. This intermediary circuit acts as a mediator between the high-gain amplifier and the final output, capturing and compensating for offset voltage without affecting the main signal amplification path.
2Power
If capacitance in the feedback branch is reduced, then gain is increased, but offset error grows detrimentally
Solution Approach 1:
The patent converts the harmful offset voltage into a useful component by measuring and storing it in the auto-zeroing circuit. The stored offset voltage is then used for compensation by being subtracted from the final output, thereby transforming the harmful offset error into a beneficial correction mechanism that improves overall accuracy.
Solution Approach 2:
The patent implements feedback through the auto-zeroing mechanism where the offset voltage is continuously measured, stored, and fed back for compensation. The switching circuitry enables the offset measurement capacitors to be connected to the amplifier inputs during calibration and then disconnected during signal amplification, creating a feedback loop that eliminates offset error.
Data Source
Figure 1
Figure 1A
Figure 1B
AI summary
A circuit (60) includes an amplifier (62), a bias voltage node (VCM), and a first set of switches (SINp, SINn, SOUT) configured, based on a first reset signal (RST) being asserted, to couple amplifier input nodes (VINp, VINn) to the bias voltage node and to short-circuit amplifier output nodes (VOUTn, VOUTp). First and second feedback branches (64, 66) each include a respective circuit network including parallel capacitors (CF1, CF2), with first ones of the capacitors (CF2) directly connected to the amplifier input nodes. The first and second feedback branches further include a second set of switches (SF1A, SF1C) intermediate the amplifier input nodes and second ones of the capacitors (CF1), and a third set of switches (SF1B, SF1D, SF2B, SF2D) intermediate amplifier output nodes and the capacitors. These switches selectively couple the capacitors to the amplifier input and output nodes, based on a second reset signal (RSTD) being asserted. The second reset signal is asserted for a time interval exceeding a time interval in which the first reset signal is asserted.