Charge-Balanced Power Transistor Structure for Higher Breakdown Voltage
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Solution Overview
Problem
Existing semiconductor transistors face challenges with low breakdown voltages when in the OFF state due to peak electrical fields and non-uniform electric field distribution, limiting their operational efficiency in high-voltage applications.
Innovation Solution
The implementation of a semiconductor device with a net-charge balancing mechanism, where a net charge region is used to distribute electric field strength uniformly across the device, achieved by positioning a fourth semiconductor region between the gate and source/drain terminals, and a segmented net charge region that extends between the gate and drain terminals, ensuring the net charge in the depletion region is balanced with the two-dimensional carrier channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transistor structures are used, then the device can operate in high-voltage applications, but the breakdown voltage is limited due to peak electrical fields and non-uniform electric field distribution
Solution Approach 1:
The patent introduces a net charge region with specific doping concentration and spatial distribution beneath the gate electrode. This creates localized charge compensation exactly where needed - in the depletion region under the gate - to balance the electric field without affecting other regions of the device. The net charge region's doping profile is specifically tailored to provide uniform electric field distribution only in the critical high-field area.
Solution Approach 2:
The patent modifies the electrical parameters of the semiconductor device by introducing a controlled net charge density in the depletion region. By adjusting the doping concentration and spatial extent of the net charge region, the electric field distribution parameter is transformed from peaked/non-uniform to uniform/balanced, thereby increasing breakdown voltage while maintaining device functionality.
2Reliability
If the net charge region is extended to cover the entire first semiconductor region, then the electric field distribution becomes more uniform, but the device complexity increases
Solution Approach 1:
The net charge region is segmented into multiple doping regions with different doping concentrations and spatial distributions. Instead of a single uniform net charge layer, the patent divides it into segments that can be independently optimized, allowing complex electric field control while maintaining manageable device structure and fabrication processes.
3Reliability
If a fourth semiconductor region is added to position between the gate and source/drain terminals, then the charge balance is improved, but the device complexity increases
Solution Approach 1:
The fourth semiconductor region serves multiple functions simultaneously: it provides mechanical support, establishes electrical connections, contributes to charge balance, and defines the spatial configuration of the net charge region. By making this region multi-functional, the patent reduces the need for additional separate components, thereby limiting the increase in device complexity while achieving improved charge balance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the breakdown voltage of the semiconductor device by reducing peak electrical fields and improving the uniformity of the electric field distribution, thereby increasing the device's reliability and efficiency in high-voltage applications.
Implementation Method 1
the net charge region having a net charge in a depletion region that is substantially equal to the net charge of the at least one two-dimensional channel in the first semiconductor region when the semiconductor device is in an off-state
Data Source
AI summary
A semiconductor device includes a semiconductor region having at least one two-dimensional carrier channel of a first conductivity type, the first conductivity type being one of a n-type and a p-type conductivity, the at least one two-dimensional channel having a net charge, the semiconductor region including a first semiconductor region coupled with a drain terminal and a second semiconductor region coupled with a source terminal; and a third semiconductor region of a second conductivity type electrically coupled with a gate terminal, having a gate region and a net charge region, the net charge region disposed over the first semiconductor region and having a net charge in a depletion region that is substantially equal to the net charge of the at least one two-dimensional channel in the first semiconductor region when the semiconductor device is in an off-state.