Charge-Based Nonvolatile Memory FPGA Cells
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Solution Overview
Problem
Field-programmable gate arrays (FPGAs) using static random access memory (SRAM) require frequent reprogramming upon power application due to SRAM's volatility, consuming significant power and area in integrated circuits.
Innovation Solution
Replacing SRAM memory cells and pass-gate transistors with non-volatile charge-based memory, such as ballistic-charge injection, flash, or phase-change memory cells, which can function as both memory and pass-gate transistors, eliminating the need for separate transistors and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SRAM memory cells are used in FPGAs, then the memory can be programmed and reprogrammed, but the volatility of SRAM requires frequent reprogramming upon power application, consuming significant power and area
Solution Approach 1:
The patent changes the fundamental parameter of memory volatility by replacing volatile SRAM with non-volatile charge-based memory cells. This parameter change eliminates the need for frequent reprogramming and reduces power consumption associated with maintaining memory state, directly resolving the contradiction between memory retention reliability and power consumption.
2Ease of manufacture
If SRAM memory cells and separate pass-gate transistors are used, then the FPGA can be programmed, but this increases area usage and device complexity
Solution Approach 1:
The patent merges the functions of memory cell and pass-gate transistor into a single integrated structure. The charge-based memory cell inherently provides both storage and switching functionality, eliminating the need for separate pass-gate transistors. This merging reduces area usage and simplifies the device structure while maintaining programming capability.
Solution Approach 2:
The charge-based memory cell serves multiple functions simultaneously: it acts as both a memory storage element and a pass-gate transistor for routing signals. This multi-functionality reduces the overall number of components needed in the FPGA architecture, thereby reducing area and complexity while preserving full programming capability.
3Adaptability or versatility
If SRAM memory cells are used, then the memory can be programmed, but frequent reprogramming is required which increases power consumption
Solution Approach 1:
The patent changes the volatility parameter of the memory from volatile (SRAM) to non-volatile (charge-based memory). This parameter change enables the memory to retain programmed states without continuous power, eliminating the need for frequent reprogramming while maintaining adaptability. The non-volatile nature allows the FPGA to be programmed once and retain configuration indefinitely without power consumption for maintenance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces power consumption and area usage in FPGAs, as charge-based memory is non-volatile, eliminating the need for frequent reprogramming and simplifying design by operating at lower voltages.
Implementation Method 1
charge-based memory, such as ballistic-charge injection, flash, or phase-change memory cells
Implementation Method 2
ballistic-charge injection memory cells
Implementation Method 3
phase-change memory cells
Data Source
AI summary
A field-programmable gate-array (FPGA) includes a first memory cell having (i) a plurality of states, (ii) a first end, and (iii) a second end; a first configurable logic block (CLB) having an output directly coupled to the first end of the first memory cell; a second memory cell having (i) a plurality of states, (ii) a first end, and (iii) a second end; and a second CLB having an input directly coupled to the first end of the second memory cell. The output of the first CLB communicates with the input of the second CLB via (i) the second end of the first memory cell and (ii) the second end of the second memory cell based on (i) the state of the first memory cell and (ii) the state of the second memory cell. Each of the first memory cell and the second memory cell includes a single-transistor memory cell of nonvolatile memory.