Charge Blocking Layer Oxidation for 3D NAND Integration
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Solution Overview
Problem
Conventional three-dimensional non-volatile memory devices face challenges in increasing integration density due to high stacked layer heights and low-quality charge blocking layers, which affect device characteristics.
Innovation Solution
The semiconductor device employs a method of forming charge blocking layers by oxidizing a given thickness of the charge trap layer, reducing the height of stacked layers and improving interface quality, with first regions between tunnel insulating layers and word lines having a smaller thickness than second regions between tunnel insulating layers and interlayer insulating layers, and additional charge blocking layers are formed to enhance erase characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If open regions are filled with conductive layers after memory layer formation, then memory cells are stacked, but the height of stacked layers increases, making it difficult to improve integration degree
Solution Approach 1:
The charge blocking layer is formed by oxidizing the charge trap layer before the conductive layer is deposited. This preliminary formation of the charge blocking layer with appropriate thickness control enables subsequent conductive layer deposition without requiring excessive vertical space, thus reducing the overall stacked layer height while maintaining integration density
Solution Approach 2:
The thickness of the charge blocking layer is precisely controlled by adjusting the oxidation conditions and duration. By optimizing these parameters, the charge blocking layer achieves the required electrical characteristics with minimal thickness, thereby reducing the height of stacked layers and improving integration degree
2Reliability
If chemical vapor deposition is used to form charge blocking layer, then memory device can be manufactured, but the charge blocking layer has low quality, deteriorating device characteristics
Solution Approach 1:
The chemical vapor deposition process is replaced with an oxidation process to form the charge blocking layer. This substitution eliminates the quality issues associated with CVD while maintaining manufacturability, as the oxidation process naturally produces high-quality, uniform layers with excellent electrical characteristics
Solution Approach 2:
The manufacturing approach changes from depositing material (CVD) to transforming existing material through oxidation. By controlling oxidation parameters such as temperature, time, and atmosphere, the charge blocking layer achieves superior quality with improved interface characteristics and reduced defects
3Reliability
If uniform thickness charge trap layer is used, then manufacturing is simplified, but interface characteristics between charge trap layer and word lines/interlayer insulating layers are suboptimal
Solution Approach 1:
The charge trap layer is differentially oxidized to create regions with different thicknesses. The first regions (between tunnel insulating layer and word lines) have smaller thickness, while the second regions (between tunnel insulating layer and interlayer insulating layers) have larger thickness. This local variation optimizes interface characteristics at different locations without requiring complete redesign of the entire layer structure
Solution Approach 2:
The selective oxidation of the charge trap layer is performed before conductive layer deposition. This preliminary differentiation of the charge trap layer thickness creates optimized interfaces in advance, ensuring that subsequent manufacturing steps proceed smoothly without requiring additional complex processing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the height of stacked layers, enhances integration density, and improves the quality of charge blocking layers and interface characteristics, leading to better operating characteristics of the memory device.
Implementation Method 1
forming first charge blocking layer patterns by oxidizing a given thickness of the charge trap layer exposed in regions from which the first material layers are removed
Data Source
AI summary
A semiconductor device includes word lines and interlayer insulating layers alternately stacked over a substrate, vertical channel layers protruding from the substrate and passing through the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding each of the vertical channel layers, a charge trap layer surrounding the tunnel insulating layer, wherein first regions of the charge trap layer between the tunnel insulating layer and the word lines have a thickness smaller than a thickness of second regions thereof between the tunnel insulating layer and the interlayer insulating layers, and first charge blocking layer patterns surrounding the first regions of the charge trap layer.