Charge Compensation Pillar Structure for Semiconductor Edge Termination
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Solution Overview
Problem
Semiconductor devices with charge compensation structures face high switching losses due to stored charge and output capacitance, which are exacerbated by the edge-termination structure, leading to increased costs and inefficiencies.
Innovation Solution
The semiconductor device incorporates a semiconductor body with alternating n-type and p-type pillar regions in both the active and peripheral areas, forming pn-junctions and an intrinsic semiconductor region in the peripheral area, which reduces switching losses by optimizing the electric field distribution and doping concentrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If charge compensation structures are implemented in the active area, then on-state resistance is reduced, but switching losses increase due to stored charge removal
Solution Approach 1:
The patent segments the device into active area and peripheral area, with the charge compensation structure located only in the peripheral area. This segmentation allows the active area to maintain low on-state resistance while the peripheral area's compensation structure reduces stored charge, thereby resolving the contradiction between low on-state resistance and low switching losses
Solution Approach 2:
The patent applies different doping configurations to different regions: the active area has optimized doping for low on-state resistance, while the peripheral area has charge compensation structures for reduced stored charge. This local differentiation allows each region to optimize its function, resolving the contradiction between on-state resistance and switching losses
2Strength
If edge-termination structures are used to achieve high breakdown voltages, then breakdown voltage is improved, but chip area increases and switching losses are exacerbated
Solution Approach 1:
The patent merges the edge-termination function with the charge compensation structure in the peripheral area. The alternating n-type and p-type pillar regions serve both as charge compensation elements and as edge-termination structures, eliminating the need for separate edge-termination structures and reducing chip area while maintaining high breakdown voltage
Solution Approach 2:
The pillar regions in the peripheral area perform multiple functions: they provide charge compensation to reduce stored charge, serve as edge-termination structures to achieve high breakdown voltage, and contribute to reducing switching losses. This multi-functionality resolves the contradiction between breakdown voltage and chip area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces switching losses by up to a factor of 10 while maintaining high breakdown voltages, as demonstrated by numerical simulations, and minimizes the impact of the edge-termination structure on device performance.
Implementation Method 1
Between adjacent first pillar regions and second pillar regions a respective pn-junction is formed
Implementation Method 2
The first pillar regions are in Ohmic contact with the drain metallization. The second pillar regions of the active area are in Ohmic contact with the source metallization
Data Source
AI summary
A charge-compensation semiconductor device includes a semiconductor body including a first surface, a second surface arranged opposite to the first surface, an edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, a drain region of a of a first conductivity type extending to the second surface, an active area, and a peripheral area arranged between the active area and the edge, a source metallization arranged on the first surface, and a drain metallization arranged on the drain region and in Ohmic contact with the drain region. In a vertical cross-section substantially orthogonal to the first surface the charge-compensation semiconductor device further includes: an equipotential region in Ohmic contact with the drain metallization and arranged in the peripheral area and next to the first surface, a low-doped semiconductor region arranged in the peripheral area and having a first concentration of dopants, and a plurality of first pillar regions alternating with second pillar regions in the active area and the peripheral area. The first pillar regions having a second concentration of dopants of the first conductivity type higher than the first concentration and are in Ohmic contact with the drain region. The second pillar regions are of a second conductivity type and in Ohmic contact with the source metallization. At least one of an outermost of the first pillar regions and an outermost of the second pillar regions forms an interface with the low-doped semiconductor region. A horizontal distance between the interface and the equipotential region divided by a vertical distance between the first surface and the drain region is in a range from about 0.5 to about 3.