Charge-Compensation Semiconductor Device with Dual Field-Stop Regions
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Solution Overview
Problem
Conventional semiconductor devices with charge-compensation structures face high switching losses due to stored charge and electric energy, leading to trade-offs between on-state resistance and switching performance, especially when operating at voltages below rated breakdown voltages.
Innovation Solution
The semiconductor device incorporates a dual charge-compensation structure with field-stop regions of varying doping concentrations, allowing for optimized depletion and conduction paths, reducing stored charge and electric energy during reverse voltages, and adjusting punch-through voltage to minimize switching losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the semiconductor device is designed for rated breakdown voltage, then it can handle voltage spikes, but it is oversized for normal operating voltages resulting in higher stored charge
Solution Approach 1:
The device structure dynamically adapts to different voltage conditions. During normal operation at voltages below rated breakdown voltage, the intrinsic zone remains undepleted, limiting stored charge. During voltage spikes approaching rated breakdown voltage, the intrinsic zone depletes to provide the necessary breakdown voltage handling capability. This dynamic behavior eliminates the need to oversize the device for rare voltage spikes.
Solution Approach 2:
The intrinsic zone provides partial charge compensation - enough to handle voltage spikes when needed but not so much that it creates excessive stored charge during normal operation. This partial action approach optimizes the balance between reliability and stored charge reduction.
2Ease of manufacture
If conventional compensation structures are used, then manufacturing is simpler, but on-state resistance and switching losses cannot be optimized simultaneously
Solution Approach 1:
The doping concentration parameter is changed across different zones of the drift region. The first and second doped zones have higher doping concentrations for charge compensation, while the intrinsic zone has zero doping. This parameter variation allows simultaneous optimization of on-state resistance and switching losses while maintaining compatibility with standard semiconductor manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces switching losses and maintains low on-state resistance, improving the trade-off between forward current losses and switching losses, even under rare voltage spikes, by precisely controlling the depletion and conduction paths.
Implementation Method 1
The compensation principle is based on a mutual compensation of charges in n- and p-doped zones in the drift region of a vertical MOSFET
Implementation Method 2
in the off-state, their charges can be mutually depleted
Implementation Method 3
adjusting punch-through voltage to minimize switching losses
Data Source
AI summary
An active area of a semiconductor body includes a first charge-compensation structure having spaced apart n-type pillar regions, and an n-type first field-stop region of a semiconductor material in Ohmic contact with a drain metallization and the n-type pillar regions and having a doping charge per area higher than a breakdown charge per area of the semiconductor material. A punch-through area of the semiconductor body includes a p-type semiconductor region in Ohmic contact with a source metallization, a floating p-type body region and an n-type second field-stop region. The floating p-type body region extends into the active area. The second field-stop region is in Ohmic contact with the first field-stop region, forms a pn-junction with the floating p-type body region, is arranged between the p-type semiconductor region and floating p-type body region, and has a doping charge per area lower than the breakdown charge per area of the semiconductor material.