Charge Constrained Codes for NAND Flash Error Correction

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Solution Overview

Problem

Solid state storage systems, such as NAND Flash systems, face issues with error correction decoding efficiency due to high noise levels in read data, leading to reduced throughput and increased power consumption.

Innovation Solution

The implementation of charge constrained codes, which enforce rules on bit sequences to ensure error correction encoding can be performed independently and systematically, allowing for faster and more power-efficient processing by using Boolean operations instead of traditional error correction encoders.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional error correction encoding is used on noisy read data, then error correction capability is maintained, but decoding time increases and throughput drops

Engineering Contradiction:
Improveerror correction capabilityVSAvoidthroughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies charge constrained coding during the write operation to pre-condition the data, ensuring that the encoded data has bounded charge transitions. This preliminary encoding structure enables the decoder to quickly validate data integrity without extensive processing, resolving the contradiction by preparing the data in advance to minimize later decoding overhead.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent transforms the encoding approach by changing from traditional error correction codes to charge constrained codes with specific electrical charge properties. This parameter change in the encoding method allows for faster validation while maintaining error detection capability, thus improving throughput without sacrificing reliability.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If traditional error correction encoding is used on noisy read data, then error correction capability is maintained, but power consumption increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

By applying charge constrained coding during writing, the system pre-structures the data to enable rapid validation during reading. This preliminary encoding reduces the computational effort required during read operations, thereby reducing power consumption while maintaining error correction capability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent replaces complex traditional error correction encoding mechanisms with a simpler charge constrained coding system that relies on electrical charge properties rather than extensive computational processing. This substitution reduces the mechanical/computational overhead and associated power consumption during error correction operations.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Measurement precision

If extensive error correction processing is performed, then decoding accuracy is improved, but processing time increases

Engineering Contradiction:
Improvedecoding accuracyVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent changes the encoding parameters to use charge constrained codes with specific transition bounds, which inherently provide error detection capabilities. This parameter change allows for accurate decoding with minimal processing time, as the charge constraints enable quick validation without extensive computational analysis.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10185623B2Reading and writing to NAND flash memories using charge constrained codes
Publication Date: 2019.01.22 SK HYNIX MEMORY SOLUTIONS AMERICA INC
  • US10185623B2 patent drawing
  • US10185623B2 patent drawing
  • US10185623B2 patent drawing

AI summary

A charge constrained bit sequence is processed to obtain a lower bound on a number of bit errors associated with the charge constrained bit sequence. The lower bound is compared against an error correction capability threshold associated with an error correction decoder. In the event the lower bound is greater than or equal to the error correction decoder threshold, an error correction decoding failure is predicted.