Charge Controlled E-Fuse Structure for Low Current Operation
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Solution Overview
Problem
Current electrical fuses in semiconductor devices require large currents to open, leading to electro-migration reliability concerns in BEOL or MOL layers, which is a significant disadvantage in advanced IC manufacturing.
Innovation Solution
A charge-controlled electronic fuse structure is implemented using a semiconductor fin with a trench isolation, p-well, n-well, and an n-type doped charge trap section, where a stress voltage applied to the gate increases charge trapping in the gate dielectric layer, blocking carrier current flow and creating a customizable resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If metal or via-based e-fuses are used in BEOL or MOL layers, then the fuse structure can be formed in standard IC manufacturing layers, but large current is required to open the fuse leading to electro-migration reliability concerns
Solution Approach 1:
The patent replaces the conventional metal/via-based e-fuse structure with a semiconductor-based structure utilizing a MOSFET device. Instead of relying on metal film rupture through high current, the invention uses controlled breakdown of a thin semiconductor layer (e.g., oxide or nitride) between source and drain regions, achieving fuse functionality through semiconductor physics rather than metallurgy.
Solution Approach 2:
The invention changes the fundamental operating parameters by using a semiconductor layer with carefully controlled thickness (e.g., 5-50 nm) and doping characteristics. The fuse opens through controlled dielectric breakdown or avalanche multiplication at much lower current levels compared to metal fuses, fundamentally altering the current-density and failure-mechanism parameters.
2Reliability
If large current is used to open the fuse, then the fuse can be reliably activated, but electro-migration reliability concerns arise in BEOL or MOL layers
Solution Approach 1:
The patent replaces the conventional metal/via-based e-fuse structure with a semiconductor-based structure utilizing a MOSFET device. Instead of relying on metal film rupture through high current, the invention uses controlled breakdown of a thin semiconductor layer (e.g., oxide or nitride) between source and drain regions, achieving fuse functionality through semiconductor physics rather than metallurgy.
Solution Approach 2:
The invention introduces an intermediary semiconductor layer (oxide or nitride) between the source and drain regions that mediates the current flow. This intermediary layer breaks down at controlled voltage/current levels to open the fuse, preventing direct high-current stress on the metal interconnect layers and thereby eliminating electro-migration concerns in the BEOL/MOL layers.
3Power
If a thin semiconductor layer is used between source and drain regions, then the current required to open the fuse is reduced, but precise control of layer thickness and doping is required
Solution Approach 1:
The invention changes the fundamental operating parameters by using a semiconductor layer with carefully controlled thickness (e.g., 5-50 nm) and doping characteristics. The fuse opens through controlled dielectric breakdown or avalanche multiplication at much lower current levels compared to metal fuses, fundamentally altering the current-density and failure-mechanism parameters.
Solution Approach 2:
The patent employs established semiconductor fabrication techniques (atomic layer deposition, chemical vapor deposition, ion implantation) to create and dope the thin semiconductor layer. These are proven, highly-controlled processes already used throughout the IC manufacturing flow, copying the precision and repeatability of standard device fabrication to ensure consistent fuse characteristics across production.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the current required to open the fuse, enhancing reliability by allowing customized resistance and minimizing electro-migration issues, particularly beneficial for semiconductor fins where the gate structure around the fin enhances charge collection.
Implementation Method 1
A stress voltage applied to the gate increases charge trapping in the gate dielectric layer due to hot carrier injection (HCl) events in the drain extension region
Implementation Method 2
blocking carrier current flow and creating a customizable resistance
Data Source
AI summary
A structure includes a first source/drain region and a second source/drain region in a semiconductor body; and a trench isolation between the first and second source/drain regions in the semiconductor body. A first doping region is about the first source/drain region, a second doping region about the second source/drain region, and the trench isolation is within the second doping region. A third doping region is adjacent to the first doping region and extend partially into the second doping region to create a charge trap section. A gate conductor of a gate structure is over the trench isolation and the first, second, and third doping regions. The charge trap section creates a charge controlled e-fuse operable by applying a stress voltage to the gate conductor.