Charge-Based DAC Partitioning for Unit-DAC Linearity Correction
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Solution Overview
Problem
Existing digital-to-analog converters (DACs) face challenges in maintaining linearity due to gain mismatches between unit-DACs, particularly in multi-level DACs used in sigma-delta converters, which affect the accuracy and stability of analog-to-digital conversion.
Innovation Solution
A digital-to-analog converter (DAC) implementation using a summing circuit and a calculation circuit that employs a recursive nth order partitioning algorithm to cancel out integrated non-linearities caused by gain mismatches, ensuring the sum of unit-DAC inputs equals the DAC input and maintaining linearity through dynamic element matching (DEM) techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple unit-DACs are used in parallel to increase conversion capacity, then productivity is improved, but gain mismatches between unit-DACs cause non-linearities that worsen measurement precision
Solution Approach 1:
The patent applies preliminary action by calculating and storing the ideal partitioning of DAC input values to unit-DACs before actual conversion occurs. The calculation circuit pre-determines how to distribute the input value among unit-DACs to compensate for their gain mismatches, using previously stored mismatch characterization data. This pre-computation ensures that even with mismatched unit-DACs, the combined output maintains high linearity without requiring real-time complex adjustments during conversion.
2Measurement precision
If dynamic element matching techniques are applied to cancel non-linearities, then measurement precision is improved, but device complexity increases due to additional calculation circuits and algorithms
Solution Approach 1:
The patent segments the DAC functionality into multiple independent unit-DACs, each with its own gain characteristics. By dividing the overall conversion function into separate units, the system can individually characterize and compensate for each unit's gain mismatch through the calculation circuit. This segmentation allows the complex linearity correction to be distributed across multiple simple units rather than requiring one complex monolithic DAC, making the overall system more manageable despite the added complexity.
3Measurement precision
If recursive nth order partitioning algorithm is used to cancel integrated non-linearities, then measurement precision is improved, but loss of time increases due to multiple computation steps
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing the partitioning information that compensates for gain mismatches in unit-DACs. The calculation circuit uses previously stored mismatch characterization data to quickly determine the appropriate distribution of input values among unit-DACs, avoiding the need for complex real-time iterative computations during actual conversion operations. This pre-computation approach maintains high linearity correction while significantly reducing the time penalty that would otherwise be incurred by recursive nth order partitioning algorithms executed in real-time.
Data Source
AI summary
A method includes receiving samples of digital to analog converter (DAC), partitioning the samples to unit-DACs based upon previous partitions of inputs to the unit-DACs to cancel out integrated non-linearities of outputs of the DAC caused by the gain mismatches of the unit-DACs, including partitioning samples of DAC input to the unit-DACs through a recursive nth order partitioning algorithm. The algorithm includes, for each DAC input, determining a first partition of the DAC input that would cancel an (n−1)th order previously integrated non-linearity, adding an equivalent DAC input of the first partition to the DAC input to obtain a total DAC input, using a first order application of the total DAC input to the inputs of the unit-DACs to yield a second partition of DAC input, summing the first and second partitions generate a final partition, and, based on the final partition, computing non-linearity remainders at each order of integration.