Charge-to-Digital Timing Circuit for Low-Power Picosecond Resolution
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Solution Overview
Problem
Conventional Time-to-Digital Converters (TDCs), particularly Vernier Delay Line (VDL) solutions, face limitations in resolution, power consumption, and calibration complexity, failing to meet the requirements of high-resolution applications like cellular technology and requiring significant power and chip area.
Innovation Solution
A Charge-to-Digital Timer (CDT) apparatus and method that charges a capacitive load with a known current, ramps a voltage in discrete steps, and estimates elapsed time using a comparator and estimation unit, providing improved resolution and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If Vernier Delay Line (VDL) solution is used to achieve time difference estimation, then the device can provide time measurement capability, but the power consumption increases significantly especially at high clock frequencies
Solution Approach 1:
The patent replaces the mechanical/electrical delay line system with a charge-based measurement system. Instead of using multiple delay stages that consume power continuously, the invention uses a single capacitive element charged by a current source, where the charge accumulation time directly represents the time difference. This substitution eliminates the need for continuous power-consuming delay elements while maintaining measurement capability.
Solution Approach 2:
The patent changes the fundamental measurement parameter from voltage delay (in VDL) to charge accumulation. By integrating current over time to generate charge on a capacitor, the system transforms the time measurement into a charge quantity measurement, which can then be converted to voltage for digital conversion. This parameter change enables lower power consumption while achieving the same measurement function.
2Measurement precision
If Vernier Delay Line (VDL) with tapped delay lines is used to achieve higher resolution, then the measurement resolution improves, but the device complexity and calibration difficulty increase
Solution Approach 1:
The patent extracts the essential measurement function from the complex multi-stage delay line structure and implements it using a single capacitive element and current source. By removing the multiple tapped delay lines and their associated complexity, the invention retains the core time measurement capability while dramatically simplifying the device structure and eliminating calibration requirements.
3Measurement precision
If conventional CDT with discrete components and separate flash ADC is used, then the basic time measurement function is achieved, but the chip area and device integration are suboptimal
Solution Approach 1:
The patent merges the charge-to-digital conversion function directly into the timing measurement circuitry. Instead of using a separate flash ADC as in conventional CDT designs, the invention integrates the ADC functionality with the charge measurement node, allowing the same capacitive element to serve both as the time measurement storage and as the input to the digital conversion process. This integration reduces chip area while maintaining measurement precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The CDT achieves resolutions between 4 ps and 8 ps with reduced power consumption and chip area, offering better performance and easier calibration compared to conventional TDCs, suitable for applications like digital phase-locked loops.
Implementation Method 1
charges a capacitive load of the voltage stepping unit with a known current between the start and stop signals to generate a load voltage based on the charged capacitive load
Data Source
AI summary
The charge-to-digital timer apparatus and method disclosed herein estimates the elapsed time between two signals, e.g., a start signal and a stop signal. To that end, at least a capacitive load is charged with a known current to generate a load voltage. Subsequently, a first voltage is ramped in a plurality of discrete voltage steps associated with a plurality of known capacitances until the ramped voltage satisfies a predetermined criterion relative to a second voltage. The elapsed time is determined from the discrete voltage steps, one of the first and second voltages, the known current, and the known capacitive load.