Charge/Discharge Control Circuit Reverse Connection Protection
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Solution Overview
Problem
Existing battery devices are not designed to protect against reverse connection states, which can cause excessive current flow and damage, and adding a separate protection circuit increases device size.
Innovation Solution
A charge/discharge control circuit with a NMOS transistor and a parasitic bipolar transistor configuration that communicates the discharge control terminal and voltage detection terminal, allowing the battery device to protect itself from reverse connection without an external protection circuit by turning off the NMOS transistor when a reverse connection is detected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate protection circuit is added to protect against reverse connection, then protection reliability is improved, but device size increases
Solution Approach 1:
The patent merges the reverse connection protection function into the existing charge/discharge control circuit by utilizing the parasitic bipolar transistor already present in the NMOS transistor structure. The protection function is combined with the charge control FET and discharge control FET circuits, eliminating the need for a separate protection circuit while maintaining protection reliability.
Solution Approach 2:
The charge/discharge control circuit is designed to perform multiple functions: normal charge/discharge control and reverse connection protection. The parasitic bipolar transistor is configured to serve both as part of the NMOS transistor structure and as a protection element that activates during reverse connection to limit current flow.
2Reliability
If reverse connection protection is implemented, then protection against excessive current is improved, but circuit complexity increases
Solution Approach 1:
The circuit utilizes the parasitic bipolar transistor that inherently exists within the NMOS transistor structure. During reverse connection, the parasitic bipolar transistor automatically activates to limit current flow without requiring external control signals or additional control logic, making the protection mechanism self-activating and minimizing added complexity.
Solution Approach 2:
The patent converts the harmful parasitic bipolar transistor effect (which normally causes unwanted current flow) into a beneficial protection mechanism. By intentionally configuring the parasitic bipolar transistor with appropriate emitter and base connections, the harmful leakage current becomes a useful protection feature that limits excessive current during reverse connection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The battery device is protected from excessive current in reverse connection states without a separate protection circuit, maintaining operational safety and reducing device size by integrating the protection mechanism within the charge/discharge control circuit.
Implementation Method 1
a parasitic bipolar transistor configured to limit a current flowing from the voltage detection terminal to the second power supply voltage input terminal
Data Source
AI summary
Provided is a technology capable of protecting a charge/discharge control circuit and a battery device from a reverse connection state without a separately provided protection circuit. The charge/discharge control circuit to be contained in a battery device including a secondary cell, an external positive terminal and an external negative terminal, and FETs which control charging and discharging of the secondary cell, respectively, includes: VDD and VSS terminals; a charge control terminal; a discharge control terminal; a voltage detection terminal to which a voltage applied to the external positive terminal is supplied; an NMOS transistor communicates the discharge control terminal and the voltage detection terminal; and a bipolar transistor having a collector to be connected to a drain of the NMOS transistor, an emitter to be connected to a source of the NMOS transistor, and a base to be connected to a bulk of the NMOS transistor and the VSS terminal.