Charge/Discharge Switch Circuit for Integrated Circuits
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Solution Overview
Problem
Conventional integrated circuit circuits experience glitches and reduced headroom due to charge injection from parasitic capacitance when switching between charge and discharge modes, which is exacerbated by the size of switch devices and the difficulty in implementing cascode devices with reduced transistor sizes and voltage supply levels.
Innovation Solution
The implementation of a charge/discharge switch circuit where switching transistors are removed from the main current path and only appear in dummy paths, allowing full-swing signal driving and smaller transistor sizing without headroom constraints, with cascode transistors performing both cascode and switching functions to minimize glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If switch devices are made smaller to reduce charge injection and glitch size, then glitch is reduced, but headroom for bias and cascode devices is reduced and switch resistance increases
Solution Approach 1:
The circuit is divided into separate charge and discharge paths with dedicated switches (first switch for charge, second switch for discharge) that operate independently. This segmentation allows each switch to be optimized for its specific function without compromising the other path, enabling smaller switch sizes that reduce charge injection while maintaining adequate headroom through the separated architecture.
Solution Approach 2:
The patent introduces a temporal dimension to the switching operation by implementing non-overlapping control signals that sequentially activate charge and discharge paths. This dimensional approach allows switches to be smaller since they only need to handle one direction at a time, reducing simultaneous headroom requirements while minimizing charge injection through reduced switch size.
2Productivity
If transistor sizes are reduced to improve integration, then device density increases, but cascode devices become more difficult to implement due to reduced headroom
Solution Approach 1:
The charge and discharge functions are segmented into separate paths with dedicated switches, allowing each transistor to be sized independently for optimal density. This segmentation enables reduced transistor sizes while maintaining cascode structure integrity in each path, as the cascode devices only need to handle one direction of current flow at a time rather than both directions simultaneously.
3Ease of operation
If bias device is turned off and on by switching to control current flow, then charge/discharge control is achieved, but a large glitch occurs on transition
Solution Approach 1:
The switching function is extracted from the bias device and implemented through dedicated first and second switches that control the charge and discharge paths separately. This extraction allows the bias device to remain continuously on, providing stable bias current without the large transition glitches that occur when the bias device itself is switched on and off.
Solution Approach 2:
Dedicated first and second switches act as intermediaries between the control signals and the bias device, allowing charge and discharge control to be achieved through these intermediary switching elements rather than directly through the bias device. This intermediary approach isolates the bias device from switching transients, eliminating large transition glitches while maintaining effective charge/discharge control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces glitches at the capacitor node, maintains adequate headroom, and improves analog performance by moving the switching effect away from the sensitive node, enabling smaller transistor sizes and efficient switching operations.
Implementation Method 1
there may still be charge injection associated with the parasitic capacitance of the switches into a node at a terminal of the capacitor when switching from a charge mode to a discharge mode or vice-versa
Data Source
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AI summary
A circuit for implementing a charge/discharge switch in an integrated circuit is described. The circuit comprises a supply bias path (203) coupled to a first node (204), wherein the supply bias path provides a charging bias current to the first node; a charge transistor (206) connected between the first node and a first terminal (212) of a capacitor (202); a charge switch (250) coupled between the first node and a ground potential (GND), wherein the charge switch enables charging of the capacitor by way of the first node; a discharge transistor (231 ) connected between the first terminal of the capacitor and a second node; a discharge switch (270) coupled between the second node (236) and a reference voltage, wherein the discharge switch enables discharging of the capacitor by way of the second node; and a ground bias path (232) coupled between the second node and ground, wherein the ground bias path provides a discharging bias current to the second node. A method of implementing a charge/discharge switch in an integrated circuit is also described.