Charge-Domain Compute-in-DRAM for High-Throughput Binary Neural Networks
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Solution Overview
Problem
Deep neural networks (DNNs) using traditional processor-based processing result in high power consumption and low throughput due to frequent reads and writes from dynamic random-access memory (DRAM), while in-memory computing is not typically applied to DRAM devices.
Innovation Solution
Implementing in-DRAM computation in the charge domain using analog computation for binary neural networks (BNNs), where weights are represented by word-lines and input parameters are stored in multibit cells, enabling high parallelism and reducing extraneous reads and writes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional processor-based processing is used for deep neural networks, then computational accuracy is maintained, but power consumption increases and throughput decreases due to frequent memory reads and writes
Solution Approach 1:
The patent merges the memory function and computation function into a single integrated structure. Memory cells store both data and weight values, and the same memory infrastructure is used to perform multiply-accumulate operations. This eliminates the need for separate processor-memory units and their associated data transfer operations, directly reducing power consumption and increasing throughput by keeping all operations within the memory array.
Solution Approach 2:
The patent introduces sense amplifiers as intermediary components that facilitate computation within the memory array. These sense amplifiers act as mediators between the stored data/weights and the output, enabling analog multiply-accumulate operations to be performed directly in the memory cells without requiring traditional processor intervention, thus reducing the computational burden on external processors.
2Productivity
If traditional processor-based processing is used for deep neural networks, then computational accuracy is maintained, but the number of memory operations increases
Solution Approach 1:
The patent combines storage and computation functions into the same memory infrastructure. Weight values and input data are both stored in memory cells, and the memory array itself performs the multiplication and accumulation operations. This eliminates the need for separate processor units and their associated memory read/write operations, significantly reducing the total number of memory operations required.
3Use of energy by moving object
If in-DRAM computation is implemented using analog computation for binary neural networks, then power efficiency and throughput are improved, but computational precision may be reduced
Solution Approach 1:
The patent changes the computational domain from digital to analog by representing weight values and input data as voltage levels or charge states in memory cells. The multiply-accumulate operations are performed through analog circuit operations (current summation, voltage multiplication) rather than digital logic operations. This parameter change enables computation to occur directly in the memory array, dramatically improving power efficiency while maintaining sufficient precision for binary neural network applications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly improves power efficiency and throughput by performing computations directly in DRAM, leveraging its high density and parallelism, thus minimizing CPU-based extraneous operations.
Implementation Method 1
a first group of DRAM memory cells are loaded with input parameters... a second group of DRAM memory cells are loaded with weight values
Implementation Method 2
a sense amplifier is activated with a third group of DRAM memory cells... the column then generates the result of the BNN compare in the charge domain
Implementation Method 3
perform computations directly in DRAM, leveraging its high density and parallelism... in the charge domain using analog computation
Data Source
AI summary
Methods and systems for computing in-dynamic random access memory (DRAM) computing include loading a first group of cells of the DRAM with input parameters and loading a second group of cells of the DRAM with inverted input parameters that are each complementary to corresponding input parameters. An offset group of cells of the DRAM is loaded with an indication of an offset voltage. An operation is performed on weights with corresponding stored input parameters or the stored inverted input parameters, and a column of the first group and the second group is activated to perform an accumulation of the operations of weights for cells in the column to store a sum. An offset voltage is generated using the indication, and an output is generated based on the comparison of the sum and the offset voltage and is stored in an output group of cells of the DRAM.