Charge-Domain MAC Unit for Multi-Bit Precision In-Memory Computing
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Solution Overview
Problem
In-memory computing designs face limitations in precision and accuracy due to non-idealities such as IR drop and manufacturing variability, particularly in current domain techniques, while charge domain designs struggle with energy efficiency and slower multi-cycle operations for multi-bit precision.
Innovation Solution
A charge domain CIM module design that performs bitwise multiplication in the digital domain, using capacitive coupling for accumulation and sample-and-hold circuits to manage bit significance, followed by a successive approximation register (SAR) ADC for digitization, enhancing precision and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If charge sharing techniques are used for in-memory computing, then energy efficiency is improved, but precision and accuracy deteriorate due to non-idealities such as IR drop and manufacturing variability
Solution Approach 1:
The patent segments the weight value into multiple bits (e.g., 2-bit weights) and stores them in separate memory locations within the bitcell array. This segmentation allows for more precise representation of weight values while maintaining energy efficiency through the charge domain approach. Each segment can be independently controlled and read, reducing the impact of IR drop and manufacturing variability on overall precision.
Solution Approach 2:
The patent applies different operations to different parts of the computation: charge domain techniques are used for multiplication and accumulation operations where energy efficiency is critical, while digital domain techniques are used for the final MAC result calculation where precision is paramount. This local quality approach optimizes both energy efficiency and precision in their respective domains.
2Measurement precision
If multi-bit precision is implemented in charge domain designs, then precision is improved, but energy consumption increases and operation speed decreases due to multi-cycle requirements
Solution Approach 1:
The patent performs preliminary actions by pre-storing segmented weight values in the memory array before computation. The weight bits are organized and ready in memory locations, allowing for efficient multi-bit operations without requiring multiple memory access cycles. This preliminary organization enables single-cycle MAC operations with multi-bit precision, avoiding the energy and time penalties of multi-cycle operations.
Solution Approach 2:
The patent uses copying by replicating weight bits across multiple memory locations in a structured manner. Each weight bit is copied to specific locations that enable parallel charge sharing operations. This copying strategy allows multi-bit weights to be processed simultaneously through charge domain techniques, achieving multi-bit precision without proportionally increasing energy consumption or operation cycles.
3Device complexity
If conventional charge sharing techniques are used, then device complexity is reduced, but manufacturing precision deteriorates due to sensitivity to process variations
Solution Approach 1:
The patent segments weight values into multiple bits stored in separate memory locations, which reduces the sensitivity to manufacturing variations. Instead of relying on a single large capacitor with precise characteristics, the segmented approach uses multiple smaller units whose combined effect achieves the desired precision while being more tolerant of process variations. This maintains simple device structure while improving manufacturing precision.
Solution Approach 2:
The patent incorporates feedback mechanisms where the results of charge sharing operations are read back and used to adjust subsequent operations. This feedback allows the system to compensate for manufacturing variations and non-idealities, improving manufacturing precision without significantly increasing device complexity. The feedback loop enables error correction and calibration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves higher precision and energy efficiency by accurately representing multi-bit inputs and weights with reduced energy consumption and faster processing times compared to conventional charge sharing techniques.
Implementation Method 1
using capacitive coupling for accumulation
Implementation Method 2
followed by a successive approximation register (SAR) ADC for digitization
Data Source
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AI summary
Multiply-accumulate (MAC) operations using In-Memory Computing are disclosed. An example apparatus includes a bitcell array to perform a MAC operation using a multibit weight and a multibit input. Each bitcell of the bitcell array includes a memory unit to store a weight bit, a multiplication unit to multiply the weight bit by an input bit, and an output capacitor to store the result. Sample-and-hold circuits coupled to each column of output capacitors are used to store a charge to a holding capacitor representing a partial MAC result for the column. Input bits are sent to the bitcell array to be multiplied by the multibit weights in a series of input cycles to generate the MAC result. Input bit significance is represented by reducing the charge stored to the holding capacitors by half at each input cycle, and weight bit significance is represented by the position of the holding capacitor.