Charge-Domain SRAM IMC Circuit With Reconfigurable MAC Precision
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Solution Overview
Problem
Conventional in-memory computing (IMC) circuits face tradeoffs among computing accuracy, memory density, and precision configurability, limiting their effectiveness in deep convolutional neural networks (CNNs).
Innovation Solution
A charge-domain IMC circuit with a compact memory structure and reconfigurable semi-parallel computing scheme is developed, utilizing a cluster of 6T SRAM cells, a charge-domain multiply-and-accumulate (MAC) circuit, and a local bit-line connected to a MOS transistor, along with an analog-to-digital converter (ADC) featuring a ring oscillator and voltage-to-time converter, enabling support for multiple levels of input activations and weights.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional in-memory computing circuits are used, then basic computing functions are achieved, but computing accuracy is limited
Solution Approach 1:
The patent divides the in-memory computing circuit into distinct functional segments: 6T SRAM cells for memory storage, MAC circuits for multiply-accumulate operations, and ADC circuits for analog-to-digital conversion. This segmentation allows each component to be optimized independently for its specific function, improving overall computing accuracy while managing complexity through modular design.
Solution Approach 2:
The patent implements reconfigurable MAC circuits that can dynamically adjust their operation modes and precision levels. The circuit can switch between different computing configurations and precision settings, enabling adaptive optimization of computing accuracy based on specific application requirements without requiring complete circuit redesign.
2Quantity of substance
If memory density is increased, then more data can be stored, but computing precision configurability is reduced
Solution Approach 1:
The 6T SRAM cells serve multiple functions: they act as memory storage elements and simultaneously function as computing units in the MAC circuit. This multi-functionality allows the same physical structure to support both high memory density and configurable precision computing, as the cells can be programmed to operate in different modes without requiring separate dedicated structures.
Solution Approach 2:
The patent employs parameter changes in the MAC circuit configuration to achieve different precision levels. By adjusting operational parameters such as voltage levels, timing sequences, and circuit activation patterns, the system can configure precision dynamically while maintaining the same physical memory structure, thus preserving both memory density and adaptability.
3Measurement precision
If computing accuracy is improved, then better AI performance is achieved, but energy consumption increases
Solution Approach 1:
The in-memory computing architecture performs computing operations directly within the memory array, eliminating the need to move data between separate memory and processing units. This self-service approach reduces energy consumption associated with data transfer while maintaining high computing accuracy through the integrated MAC operations and ADC conversion.
Solution Approach 2:
The reconfigurable MAC circuits can dynamically adjust their operational precision and activation levels based on computational requirements. This dynamic adaptation allows the system to use higher precision configurations only when necessary for accurate AI computations, while using lower precision modes for less critical operations, thereby optimizing the balance between computing accuracy and energy consumption.
4Device complexity
If circuit complexity is reduced, then manufacturing becomes easier, but precision configurability is limited
Solution Approach 1:
The patent achieves precision configurability primarily through parameter changes in the MAC circuit operation rather than through complex physical reconfiguration. By controlling operational parameters such as voltage levels, timing sequences, and switch states, the system can achieve multiple precision levels using a relatively simple and uniform circuit structure, thus maintaining ease of manufacture while providing adaptability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances computing accuracy, memory density, and precision configurability, supporting both 2's complement and ternary encodings, while reducing circuit complexity and energy consumption, as demonstrated by the test chip results.
Implementation Method 1
The LBL is connected to a gate of the MOS transistor. A first terminal of the MOS transistor is connected to a DC voltage, and a second terminal of the MOS transistor is connected to the output port via the output switch. The second terminal of the MOS transistor is connected to the input port via the input switch.
Implementation Method 2
The second terminal of the MOS transistor is connected to a first side of the capacitor. A second side of the capacitor is grounded.
Implementation Method 3
an analog-to-digital converter (ADC) featuring a ring oscillator and voltage-to-time converter
Implementation Method 4
an analog-to-digital converter (ADC) featuring a ring oscillator and voltage-to-time converter (VTC)
Data Source
AI summary
A charge-domain IMC circuit is disclosed and includes: a cluster of 6T SRAM cells; a charge-domain MAC circuit; and an LBL connected to a bit-line of each of the 6T SRAM cells. The MAC circuit includes: a MOS transistor; an input switch; an output switch; an input port; an output port; and a capacitor. The LBL is connected to a gate of the MOS transistor. A first terminal of the MOS transistor is connected to a DC voltage, and a second terminal of the MOS transistor is connected to the output port via the output switch. The second terminal of the MOS transistor is connected to the input port via the input switch and to a first side of the capacitor. A second side of the capacitor is grounded. Other variants of the IMC circuit are disclosed, some of which having a ciSAR ADC or a TD-ADC.