3D Charge Storage Layer Isolation for Reliable NAND Integration
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Solution Overview
Problem
Current semiconductor devices face challenges in enhancing the degree of integration and reliability, particularly with conventional planar transistor structures, which limit their performance and efficiency.
Innovation Solution
The semiconductor device incorporates vertically stacked gate electrodes, interlayer insulating layers, channel structures with tunneling and charge storage layers, and blocking insulating layers, forming a complex structure that improves integration and reliability by optimizing the arrangement and manufacturing process of these components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If charge storage layers are used to increase integration density, then data storage capacity is improved, but charge spreading occurs causing electrical characteristic degradation
Solution Approach 1:
Blocking insulating layers are introduced as intermediary structures between adjacent charge storage layers. These blocking layers prevent direct electrical interaction and charge spreading between neighboring storage regions, thereby maintaining electrical characteristic reliability while allowing high integration density through the presence of multiple charge storage layers
Solution Approach 2:
The charge storage system is segmented into discrete, isolated units by introducing blocking insulating layers between adjacent charge storage layers. This segmentation prevents charge spreading across the entire array and confines electrical characteristics to individual storage regions, enabling reliable operation at high integration densities
2Quantity of substance
If more charge storage layers are stacked vertically, then integration density increases, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar (2D) to vertical (3D) stacking of gate electrodes and charge storage layers. By utilizing the vertical dimension, multiple charge storage layers can be accommodated within a smaller footprint area, significantly increasing integration density without proportionally increasing manufacturing complexity
Solution Approach 2:
Charge storage layers and blocking insulating layers are nested in an alternating vertical sequence, with each charge storage layer confined between blocking layers. This nested structure allows multiple functional layers to be integrated vertically while maintaining a compact overall architecture that simplifies the manufacturing process compared to lateral expansion
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the reliability and performance of semiconductor devices by increasing the degree of integration and preventing electrical characteristic degradation, such as improved retention characteristics and efficient charge storage.
Implementation Method 1
a tunneling insulating layer on the channel layer and extending perpendicularly to the upper surface of the substrate
Implementation Method 2
first blocking insulating layers on the charge storage layers, respectively... the blocking insulating layers, together with the tunneling insulating layer, may completely surround the charge storage layers
Implementation Method 3
nitriding remaining unoxidized second vertical sacrificial layers to form charge storage layers
Data Source
AI summary
Semiconductor devices are provided. A semiconductor device includes gate electrodes on a substrate and stacked perpendicularly to an upper surface of the substrate. The semiconductor device includes interlayer insulating layers alternately stacked with the gate electrodes. Moreover, the semiconductor device includes channel structures passing through the gate electrodes. Each of the channel structures includes a channel layer extending perpendicularly to the upper surface of the substrate, a tunneling insulating layer on the channel layer, charge storage layers on the tunneling insulating layer in respective regions between the gate electrodes and a side surface of the tunneling insulating layer, and first blocking insulating layers on the charge storage layers, respectively. A first layer of the first blocking insulating layers is on an upper surface, a lower surface, and a side surface of a first layer of the charge storage layers.