Charge-Accumulating MAC Circuit for Low-Power Neural Computing

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Solution Overview

Problem

Existing analog systems for multiply-accumulate operations face challenges in integrating circuits efficiently, leading to higher power consumption and complexity in neural networks and similar applications.

Innovation Solution

The proposed arithmetic logic unit incorporates a multiply-accumulate operation device with a weight unit, holding unit, switch unit, and accumulation unit, utilizing MOS transistors to generate and accumulate charges based on input electrical signals and weight values, allowing for easy integration and reduced power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If an analog circuit is used for multiply-accumulate operations, then power consumption is reduced, but circuit integration becomes difficult

Engineering Contradiction:

Improvepower consumptionVSAvoidcircuit integration

Core Design Contradiction:

Use of energy by moving objectVSEase of manufacture

Solution Approach 1:

The analog circuit is divided into multiple independent multiplication units, each handling a specific weight-value multiplication. These units can be independently designed and integrated, with each unit containing its own switching elements and charge storage components. This segmentation allows the complex analog circuit to be built using standard integrated circuit fabrication processes.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The multiplication units are designed with universal structures that can handle different weight values through configurable switching elements. The same basic unit architecture can be replicated and configured for different applications, making the analog circuit easily integrable with digital control logic and adaptable to various neural network configurations.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Use of energy by moving object

If an analog system is used for neural network processing, then power consumption is reduced, but device complexity increases

Engineering Contradiction:

Improvepower consumptionVSAvoiddevice complexity

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

Instead of using complex continuous analog components, the invention uses discrete charge packets that can be copied and transferred between storage elements. Each multiplication unit generates charge packets representing weight values, which are then transferred to accumulation units. This copying approach simplifies the analog circuitry while maintaining the computational functionality needed for neural network processing.

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The invention replaces complex mechanical or continuous analog computing mechanisms with electrical charge-based computation. By using charge packets that can be generated, stored, and transferred through switching elements, the system achieves analog computation functionality with simpler electrical components that are easier to integrate and control.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enables efficient integration of analog systems for multiply-accumulate operations, reducing power consumption and complexity while maintaining high precision and accuracy in neural network processing.

Implementation Method 1

The weight unit includes a MOS transistor including an input terminal, an output terminal, and a gate terminal for controlling conduction between the input terminal and the output terminal. The weight value may be set by a resistance between the input terminal and the output terminal.

Methodology Applied

Scientific EffectMOS transistor conduction control:

Implementation Method 2

an accumulation unit that accumulates the charges output to the pair of output lines by the plurality of multiplication units

Methodology Applied

Scientific EffectCharge accumulation: Capacitance

Data Source

PatentUS11782680B2Arithmetic logic unit, multiply-accumulate operation device, multiply-accumulate operation circuit, and multiply-accumulate operation system

Publication Date: 2023.10.10 SONY GROUP CORP

AI summary

An arithmetic logic unit according to an embodiment of the present technology includes: a plurality of input lines; and a multiply-accumulate operation device. Electrical signals are input to the plurality of input lines. The multiply-accumulate operation device includes a pair of output lines, a plurality of multiplication units including a weight unit that generates, on the basis of the electrical signals input to the plurality of input lines, charges corresponding to multiplication values obtained by multiplying signal values represented by the electrical signals by weight values, a holding unit that holds a binary state, and a switch unit that outputs, on the basis of the held binary state, the charges generated by the weight unit to one of the pair of output lines, an accumulation unit that accumulates the charges output to the pair of output lines by the plurality of multiplication units, and an output unit that outputs, on the basis of the accumulated charges, a multiply-accumulate signal representing a sum of the multiplication values.