Charge Pump Bias Matching for Balanced Locked Loop Control
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Solution Overview
Problem
Conventional locked loop circuits face challenges in achieving a balanced charge and discharge current due to topographical differences between the charge pump, bias generator, and voltage controlled delay line, leading to asymmetrical operation and excessive charging current at low control voltage ranges.
Innovation Solution
The proposed solution involves a bias generator and charge pump design with a parallel/series configuration of transistors, where the bias generator includes differential amplifiers and transistors connected in a manner that compensates for variations in control voltage, and the charge pump balances currents by using PMOS and NMOS transistors with complementary signals, ensuring balanced charging and discharging of the capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional charge pump and bias generator designs are used, then the circuit can operate, but the charge and discharge currents are unbalanced leading to asymmetrical operation
Solution Approach 1:
The patent intentionally introduces asymmetry in the form of different transistor sizing factors (K1, K2, K3, K4) to compensate for the inherent asymmetry in the charge pump and bias generator topologies. By making the transistor widths and lengths non-uniform, the design achieves symmetrical current balance between charging and discharging operations.
Solution Approach 2:
The patent modifies electrical parameters (transistor width-to-length ratios) to achieve current balance. Specifically, it adjusts the dimensions of transistors M1-M4 in the charge pump and M5-M10 in the bias generator to ensure that the charge current equals the discharge current across the operating range.
2Device complexity
If conventional designs are used, then the circuit structure is simple, but excessive charging current occurs at low control voltage ranges
Solution Approach 1:
The patent applies local quality by making different parts of the circuit have different transistor dimensions. Specifically, transistors in the charge pump (M1-M4) have different width-to-length ratios than those in the bias generator (M5-M10), allowing each section to be optimized for its specific function while maintaining overall current balance.
3Adaptability or versatility
If the charge pump and bias generator have different topographies, then each can be optimized for its function, but current balance is difficult to achieve
Solution Approach 1:
The patent changes the electrical parameters (transistor dimensions) to compensate for topographical differences. By carefully selecting the width-to-length ratios of transistors M1-M10, the design achieves current balance despite the different circuit topologies of the charge pump and bias generator sections.
Data Source
AI summary
Locked loops, bias generators, charge pumps and methods for generating control voltages are disclosed, such as a bias generator that generates bias voltages for use by a clock signal generator, such as a voltage controlled delay line, in a locked loop having a phase detector and a charge pump. The charge pump can either charge or discharge a capacitor as a function of a signal from the phase detector to generate a control voltage. The bias generator can receive the control voltage from the capacitor, and it generates bias voltages corresponding thereto. A portion of the bias generator can have a topography that is substantially the same as at least a portion of the topography of the charge pump. As a result, it can cause the charge pump to charge the capacitor at the same rate that it discharges the capacitor over a relatively wide range of control voltages. The charge pump and the bias generator can also include circuitry for limiting the charging of the capacitor when the control voltage is relatively low.