Charge Pump Circuit Bootstrap Level Shifting for Voltage Generation
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Solution Overview
Problem
Existing charge pump circuits face inefficiencies due to high on-resistance in switching transistors, leading to increased voltage drops and reduced efficiency, particularly when transistor width is decreased to minimize resistance, resulting in increased charge loss and reduced output voltage multiplication.
Innovation Solution
The implementation of a bootstrap-based level shifting circuit and charge transfer switching circuit with cross-coupled transistors and capacitors, where the gate nodes of transistors are driven by specific clock signals to enhance the gate-to-source voltage (Vgs) of switching transistors, reducing on-resistance and output impedance, and achieving multiplied positive and negative output voltages efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If transistor width is decreased to minimize on-resistance, then on-resistance is reduced, but charge loss increases and output voltage multiplication is reduced
Solution Approach 1:
The patent changes the voltage parameter (Vgs) dynamically by using a bootstrap circuit to boost the gate voltage. This allows the transistor to operate with higher effective Vgs during charge transfer, reducing on-resistance without requiring increased transistor width, thereby avoiding the trade-off between resistance and charge loss
Solution Approach 2:
The bootstrap circuit performs preliminary action by pre-charging the gate node to a voltage higher than the source voltage before charge transfer begins. This ensures that the transistor is already in a low-resistance state when charge transfer starts, maximizing efficiency without increasing device dimensions
2Loss of energy
If transistor width is increased to reduce on-resistance, then on-resistance is reduced, but device area increases and charge loss increases
Solution Approach 1:
Instead of changing the physical dimension (width) of the transistor, the patent changes the electrical parameter (gate voltage) to achieve lower on-resistance. The bootstrap circuit raises the gate voltage above the source voltage, creating a larger Vgs that reduces channel resistance without requiring a wider transistor channel
3Device complexity
If conventional charge pump circuit is used, then circuit structure is simple, but voltage drops are high and efficiency is reduced
Solution Approach 1:
The patent introduces a bootstrap circuit as an intermediary component that mediates between the clock signal and the transistor gate. This intermediary boosts the gate voltage using capacitive coupling, enabling the transistor to overcome voltage drops during charge transfer without significantly complicating the overall circuit structure
Solution Approach 2:
The bootstrap circuit operates periodically in sync with the clock signal, charging the gate node during one phase and transferring charge during the next phase. This periodic action maintains efficient operation through the oscillating clock cycles while managing the added circuit complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the on-resistance of switching transistors, thereby decreasing output impedance and improving the efficiency of charge pump circuits, allowing for effective generation of multiplied positive and negative output voltages with reduced voltage drops and increased charge transfer efficiency.
Implementation Method 1
A capacitor C1 has one terminal coupled to node NA1 and another terminal coupled to receive the logical inversion of a clock signal CK
Implementation Method 2
The on-resistance (Rds_on) of the transistors MN1, MN2, MP1 and MP2 is given by the following formula
Data Source
AI summary
A charge pump includes an intermediate node capacitively coupled to receive a first clock signal oscillating between a ground and positive supply voltage, the intermediate node generating a first signal oscillating between a first and second voltage. A level shifting circuit shifts the first signal in response to a second clock signal to generate a second signal oscillating between first and third voltages. A CMOS switching circuit includes a first transistor having a source coupled to an input, a second transistor having a source coupled to an output and a gate coupled to receive the second signal. A common drain of the CMOS switching circuit is capacitively coupled to receive the first clock signal. When positively pumping, the first voltage is twice the second voltage and the third voltage is ground. When negatively pumping, the first and third voltages are of opposite polarity and the second voltage is ground.