Charge Pump Cache for Low Power Memory Transitions
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Solution Overview
Problem
Transferring control information between volatile and non-volatile memory during low power mode transitions in memory devices results in high latency and power consumption due to the need to store and retrieve this information from non-volatile storage.
Innovation Solution
A memory device configuration that includes a charge pump to power a cache during low power mode, allowing control information to be stored and retrieved from it instead of non-volatile storage, thereby reducing latency and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If control information is transferred to non-volatile storage during low power mode transitions, then power consumption is reduced, but latency increases due to the time required to store and retrieve information from non-volatile storage
Solution Approach 1:
The patent segments the memory system into multiple power domains: a first power domain containing volatile memory (cache) and a second power domain containing non-volatile storage. This segmentation allows selective powering of components - the volatile cache remains powered in the first domain while the non-volatile storage is powered down in the second domain during low power mode, enabling fast access to control information without requiring transfers to slow non-volatile storage
Solution Approach 2:
The patent introduces a volatile cache memory as an intermediary between the processor and non-volatile storage. This cache acts as a buffer that can be kept in a powered state during low power mode transitions, providing fast access to control information and eliminating the need for frequent reads/writes to non-volatile storage, thus reducing both power consumption and latency
2Speed
If control information is stored in volatile memory during low power mode, then access speed is improved, but power consumption increases due to the need to maintain volatile memory powered
Solution Approach 1:
The patent divides the memory system into separate power domains, allowing the volatile cache to be powered independently from the non-volatile storage. During low power mode, only the essential volatile cache is powered in the first power domain, while the second power domain is powered down. This segmentation enables the system to maintain fast access speeds for control information while minimizing overall power consumption by powering down non-essential components
Solution Approach 2:
The patent applies different power states to different parts of the memory system based on their specific requirements. The volatile cache, which requires fast access, is maintained in a powered state locally, while the non-volatile storage, which can tolerate slower access, is powered down. This local differentiation of power quality allows the system to optimize both speed and power consumption simultaneously
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the overall latency and power efficiency of memory devices by allowing control information to be stored and retrieved from the cache during low power mode transitions, reducing the need for frequent transfers to and from non-volatile storage.
Implementation Method 1
a charge pump that is configured to convert a voltage associated with the second power domain to a voltage associated with the first power domain
Data Source
AI summary
Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.