Charge Pump Clock Buffer Power Control for Ripple Reduction
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Solution Overview
Problem
Existing charge pump designs face challenges in reducing current consumption and output voltage ripple, particularly in generating operating voltages for non-volatile memory systems, which are essential for efficient and reliable memory operations.
Innovation Solution
A charge pump system incorporating a regulation circuit and clock buffer with level-controlled inverters, where the feedback signal directly adjusts the power level to the clock buffer, allowing immediate control over the clock buffer's power consumption and output voltage, thereby reducing ripple and improving power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional charge pump designs are used to generate operating voltages, then voltage generation function is achieved, but current consumption is high
Solution Approach 1:
The clock buffer's power supply voltage is made dynamically adjustable through the clamp circuit, which modulates the voltage level based on operating conditions. This dynamic power control allows the charge pump to reduce current consumption when full power is not needed, while maintaining voltage generation reliability when required.
Solution Approach 2:
The invention changes the power supply voltage parameter of the clock buffer by utilizing the clamp circuit to adjust the voltage level. By varying this parameter, the system optimizes the trade-off between current consumption and voltage generation stability, achieving lower power usage without sacrificing operational reliability.
2Stability of the object's composition
If clock buffer power level is increased to improve voltage generation, then voltage output stability is improved, but power consumption increases
Solution Approach 1:
The clamp circuit enables dynamic adjustment of the clock buffer's power supply voltage parameter. By modulating this parameter, the system achieves optimal output voltage stability only when necessary, rather than maintaining high power levels continuously, thus reducing overall power consumption while preserving voltage stability during operation.
Solution Approach 2:
The power supply voltage to the clock buffer is made dynamic through the clamp circuit's voltage modulation capability. This allows the system to adapt the power level to actual operating needs, maintaining voltage stability during charge pump operation while minimizing power consumption during idle or low-demand periods.
3Object-generated harmful factors
If conventional clock buffers are used, then clock signal generation is achieved, but output voltage ripple is high
Solution Approach 1:
The clamp circuit serves as an intermediary element between the power supply and the clock buffer. It introduces a voltage modulation mechanism that reduces output voltage ripple by controlling the power supply voltage to the buffer, achieving ripple reduction without requiring complex buffer circuit redesign.
Solution Approach 2:
By changing the power supply voltage parameter of the clock buffer through the clamp circuit, the system reduces output voltage ripple. This parameter adjustment approach achieves ripple mitigation without increasing the structural complexity of the buffer circuit itself, maintaining a relatively simple overall design.
Data Source
AI summary
A charge pump system includes a charge pump that receives its clock signals, generated by an oscillator circuit, though a clock buffer. The clock buffer is power-controlled to reduce power consumption and output voltage ripple. The buffer is formed of a series of inverter that are connected to the power supply level through a clamping element, such as a transistor whose gate is controlled by a regulation signal based on feedback from the pump's output.