Charge Pump Circuit Clock Driver Transistor Sizing
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Solution Overview
Problem
In charge pump circuits, particularly those used in power supplies for CCDs, the large size of P-channel type MOS transistors required to reduce ON-resistance leads to inefficiencies and increased costs due to the high voltage between the gate and source when the transistors are turned on.
Innovation Solution
The use of boosted voltages generated at connecting nodes within the charge pump circuit as gate voltages for MOS transistors in clock drivers, allowing for reduced transistor sizes by maintaining a lower ON-resistance, and incorporating level shift circuits to manage voltage levels for P-channel and N-channel transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If P-channel type MOS transistors are used in clock drivers to handle high voltage, then the voltage handling capability is improved, but the transistor size and ON-resistance increase
Solution Approach 1:
The clock driver circuit is divided into two separate circuits: a first clock driver for positive voltage clocks and a second clock driver for negative voltage clocks. This segmentation allows each transistor to be optimized for its specific voltage range, reducing the size and ON-resistance requirements compared to a single P-channel transistor handling all high voltage operations.
Solution Approach 2:
Instead of using P-channel transistors for both positive and negative voltage clock drivers (which would require large sizes to handle high voltage), the invention uses N-channel transistors for the negative voltage clock driver. This inversion of the conventional approach allows smaller transistors with lower ON-resistance while still handling the required voltage levels through proper circuit configuration.
2Loss of energy
If P-channel type MOS transistors are used to reduce ON-resistance, then the conduction efficiency is improved, but the gate-source voltage requirement increases
Solution Approach 1:
The clock driver functionality is segmented into separate positive and negative voltage circuits. The N-channel transistor in the negative voltage clock driver is designed with optimized gate-source voltage characteristics that reduce ON-resistance without requiring excessively high gate voltages, unlike the conventional approach of using P-channel transistors for all high voltage applications.
Solution Approach 2:
The invention changes the transistor type parameter from P-channel to N-channel for the negative voltage clock driver. This parameter change allows for different voltage characteristics where the N-channel transistor can achieve lower ON-resistance with more manageable gate-source voltage requirements, improving overall energy efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the size and cost of MOS transistors by lowering their ON-resistance while preventing simultaneous turning on and through-currents, enhancing the efficiency and stability of the charge pump circuit's voltage boosting operation.
Implementation Method 1
a plurality of capacitors each with a first terminal connected with each of connecting nodes between the plurality of charge transfer devices respectively
Data Source
AI summary
A size of a charge pump circuit is reduced as well as its cost. In a positive booster charge pump circuit in an embodiment of this invention, a positive boosted voltage 2VDD generated at its first stage node is used as a gate voltage to turn on a MOS transistor that outputs a high level (VDD) of each of the first, third and fourth clock drivers. And in a negative charge pump circuit, a negative boosted voltage −VDD generated at its first stage node is used as a gate voltage to turn on a MOS transistor that outputs a high level of each of the second and fifth clock drivers.