Charge Pump Clock Phasing for Lower Current and Ripple Noise
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Charge pump circuits in semiconductor devices consume high input currents and have inefficiencies in voltage generation, particularly due to unnecessary switching operations and simultaneous clock transitions, which increase power consumption and ripple noise.
Innovation Solution
A semiconductor device with a charge pump circuit that includes a voltage detection circuit and a driving control circuit to manage clock transitions, ensuring the second main clock transitions after the first main clock, and storing clock logic levels at the end of the activation period to minimize simultaneous transitions and reduce current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If simultaneous clock transitions are used in charge pump circuit, then operation speed is improved, but input current consumption increases
Solution Approach 1:
The patent implements periodic clock transitions where the first main clock transitions at a first time and the second main clock transitions at a second time that is different from the first time. This time-separated periodic action reduces simultaneous switching activity, thereby reducing input current consumption while maintaining operational functionality through structured clock phasing.
2Productivity
If charge pump circuit operates continuously, then voltage generation efficiency is improved, but power consumption increases
Solution Approach 1:
The patent employs periodic action by controlling the charge pump circuit to operate only during necessary periods rather than continuously. The selective activation based on voltage detection results ensures the circuit performs voltage generation tasks efficiently when needed while remaining inactive during unnecessary periods, thereby reducing overall power consumption.
Solution Approach 2:
The patent implements feedback control through a voltage detection circuit that monitors the generated voltage and provides feedback signals to control whether the charge pump circuit should operate. This feedback mechanism enables the circuit to activate only when voltage generation is actually required, optimizing the balance between voltage generation efficiency and power consumption.
3Use of energy by moving object
If clock transitions are controlled sequentially, then input current consumption is reduced, but operation time increases
Solution Approach 1:
The patent implements periodic action by controlling the charge pump circuit to operate only during necessary periods rather than continuously. The selective activation based on voltage detection results ensures the circuit performs voltage generation tasks efficiently when needed while remaining inactive during unnecessary periods, thereby reducing overall power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces input current consumption and overall power usage while minimizing the time required for charge pump operations and reducing voltage ripple noise, thereby enhancing power efficiency.
Implementation Method 1
a charge pump circuit suitable for generating an output voltage by pumping an input voltage according to first and second main clocks
Implementation Method 2
a voltage detection circuit suitable for generating a comparison signal by comparing the output voltage with a reference voltage
Data Source
AI summary
A semiconductor device includes: a charge pump circuit configured to generate an output voltage by pumping an input voltage according to first and second main clocks, a voltage detection circuit configured to generate a comparison signal by comparing the output voltage with a reference voltage, and a driving control circuit configured to selectively invert first and second external clocks at a start time of an activation period of the comparison signal to receive the inverted clocks as first and second internal clocks, to generate the first and second main clocks according to the first and second internal clocks during the activation period while controlling a transition order so that the second main clock transitions after the first main clock transitions, and to store logic levels of the first and second main clocks, respectively, at an end time of the activation period.