Charge-Pump Clock Skipping for AFE Noise Suppression
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Solution Overview
Problem
Conventional analog front-end (AFE) systems experience deteriorated signal-to-noise ratio (SNR) due to noise introduced by the charge-pump clock, particularly through ground bounce and electromagnetic discharge, which is exacerbated by cost-driven PCB designs with single ground planes, limiting the rise/fall time of the charge-pump clock.
Innovation Solution
Implementing a duty cycle modulation of the charge-pump clock, where the first clock rises three cycles before the second, remains high for seventeen cycles, falls five cycles before the first clock falls, and is low for seventeen cycles, with a state-machine control skipping the charge-pump clock period right before the video sample signal falling edge if it runs faster than the AFE video sampling clock, aligning clock edges with ADC and video sample signals to minimize noise impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the charge-pump clock rise/fall time is increased to reduce switching noise, then the SNR improves, but the charge-pump efficiency deteriorates due to minimum clock rise/fall time constraints dictated by efficiency and shoot-through concerns
Solution Approach 1:
The patent implements a periodic skipping pattern where the charge-pump clock is selectively enabled or disabled in alternating periods. During periods when video sampling occurs, the charge-pump clock is skipped to eliminate ground bounce noise. During other periods, the charge-pump operates normally to maintain efficiency. This periodic on/off pattern resolves the contradiction by allowing the system to optimize for noise reduction when needed and for efficiency when sampling is not occurring.
2Ease of manufacture
If a single ground plane is used in PCB design to reduce cost, then manufacturing cost decreases, but ground bounce noise increases causing SNR deterioration
Solution Approach 1:
The patent extracts the charge-pump clock signal from continuous operation and removes it during critical periods when video sampling occurs. By taking out the problematic clock signal during specific time windows, the system eliminates ground bounce noise without requiring a complex multi-ground-plane PCB design, thus maintaining cost-effectiveness while improving SNR.
3Productivity
If the charge-pump clock runs faster than the AFE video sampling clock to improve productivity, then charge-pump output increases, but noise coupling to video inputs, RLC signals, and ADC references increases
Solution Approach 1:
The patent implements a skipping mechanism where the charge-pump clock is deliberately skipped or paused right before video sample falling edges. This allows the charge-pump to operate at high speeds during non-critical periods to maximize productivity, while briefly pausing during critical sampling moments to prevent noise coupling. The state-machine control detects sampling phases and selectively skips clock cycles to eliminate inter-modulation products.
Data Source
AI summary
An apparatus, comprising: a charge-pump; a sampler that samples an optical signal, including: a black sampler; a video sampler; and an analog to digital converter. The first aspect further provides a single clock that is coupled to and provides clocking signals to: a) the charge-pump logic that is coupled to the charge-pump; and b) the sampler logic that is coupled to the sampler that samples the optical signal, wherein if the clock for the charge pump is running faster than an analog front end (“AFE”) video sampling clock, a state-machine control is configured to: skip the charge pump clock period right before a video sample signal falling edge, thereby recovering to a normal operation the next charge-pump clock period, wherein this duty cycle modulation of charge pump clock will not substantially impact charge pump output.