Charge Pump Cross-Coupling Circuit Parasitic Capacitance Reduction
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Solution Overview
Problem
Integrated circuits face challenges in efficiently providing specific voltage levels to circuit blocks due to factors like parasitic capacitance and power dissipation across transistors, particularly at higher clock frequencies, which reduces charge pump efficiency.
Innovation Solution
A system and method that include a charge pump with cross-coupling capacitors and a control circuit to independently manage the operation of charge pumps based on varying operating conditions, reducing power consumption by minimizing the number of partially enabled transistors and utilizing a cross-coupling circuit to reduce parasitic bottom plate capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If charge pumps are used to generate various voltage levels, then the number of external power supplies is reduced, but parasitic capacitance and power dissipation increase particularly at higher clock frequencies
Solution Approach 1:
The patent changes the voltage parameter of the intermediate node by coupling it to the supply voltage through the cross-coupling circuit. This parameter change reduces the voltage swing at the bottom plate of the capacitor, thereby reducing parasitic capacitance effects and power dissipation during charging and discharging operations.
Solution Approach 2:
The cross-coupling circuit acts as an intermediary between the intermediate node and the supply voltage. It mediates the voltage level at the intermediate node, preventing large voltage swings that would otherwise cause excessive power dissipation and parasitic capacitance effects.
2Productivity
If charge pumps operate at higher clock frequencies to improve productivity, then voltage generation speed increases, but parasitic capacitance effects worsen and efficiency decreases
Solution Approach 1:
The patent changes the voltage parameter at the intermediate node to reduce parasitic capacitance effects. By maintaining a more stable voltage at this node through cross-coupling to the supply voltage, the effective parasitic capacitance is reduced, allowing higher clock frequencies to operate with less efficiency loss.
3Device complexity
If the intermediate node is left floating during clock operation, then circuit complexity is minimized, but parasitic capacitance at the bottom plate increases
Solution Approach 1:
The cross-coupling circuit serves as an intermediary that connects the intermediate node to the supply voltage. This additional circuit element reduces parasitic bottom plate capacitance by providing a defined voltage path, preventing the intermediate node from floating and accumulating parasitic charge.
Solution Approach 2:
The patent changes the electrical state of the intermediate node from floating to supply-voltage-coupled. This parameter change in voltage definition reduces the effective parasitic capacitance at the bottom plate of the capacitor, improving charge pump efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances charge pump efficiency by optimizing power usage and reducing parasitic capacitance, thereby improving the overall performance of integrated circuits across different operating conditions.
Implementation Method 1
factors such as parasitic capacitance and power dissipation across transistors may reduce charge pump efficiencies
Implementation Method 2
a first capacitor to charge while a first clock signal is high and a second capacitor to charge while a second clock signal is high
Data Source
AI summary
A system for providing a load current at a specific output voltage to a circuit block of an integrated circuit (IC) includes a supply node at a supply voltage, a charge pump, and a cross-coupling circuit. The charge pump includes a first a first capacitor to charge while a first clock signal is high and a second capacitor to charge while a second clock signal is high. Each of the capacitors has a top plate node, a bottom plate node, a ground node, and an intermediate node between the bottom plate node and the ground node. The cross-coupling circuit couples the intermediate node of the first capacitor to the supply node while the second clock signal is high and couples the intermediate node of the second capacitor to the supply node while the first clock signal is high.