Charge Pump Calibration for Low-Spur DLL Frequency Multiplication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional delay-locked loops (DLLs) face challenges in multiplying a reference frequency by an arbitrary integer value while minimizing noise and spurs in the output clock signal, due to the introduction of unwanted delays and difficulty in programmability of the multiplying factor.
Innovation Solution
A DLL design that employs a voltage-controlled oscillator (VCO) instead of tap-controlled delay lines, allowing for frequency multiplication by adjusting the control voltage to align selected edges of the output oscillation signal with the input oscillation signal, thereby reducing noise and spurs, and enabling programmability of the multiplying factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If tap-controlled delay lines are used for frequency multiplication, then the output signal can be delay-locked with the input signal, but unwanted delays are introduced and spurs are generated in the output clock signal
Solution Approach 1:
The patent extracts the delay function from traditional tap-controlled delay lines and implements it using a voltage-controlled oscillator (VCO) with a loop filter. This removes the source of spurs and noise associated with tap-controlled delay lines while maintaining the delay-lock functionality through voltage-controlled phase adjustment.
Solution Approach 2:
The patent replaces the mechanical/structural approach of tap-controlled delay lines with an electrical/voltage-controlled approach using a VCO. Instead of physically selecting different delay taps, the system uses voltage control to adjust the oscillator phase, eliminating mechanical switching artifacts that cause spurs.
2Reliability
If tap-controlled delay lines are used for frequency multiplication, then the output signal can be synchronized with the input signal, but programmability of the multiplying factor is difficult to implement
Solution Approach 1:
The patent implements dynamic control of the multiplying factor through voltage adjustment of the VCO. Instead of fixed delay taps, the system allows continuous or discrete adjustment of the oscillator frequency and phase through voltage control, enabling programmable frequency multiplication ratios while maintaining synchronization through feedback.
Solution Approach 2:
The patent changes the control parameter from discrete tap selection to continuous voltage control. By adjusting the control voltage to the VCO, the multiplying factor becomes programmable and adjustable, allowing flexible frequency synthesis while maintaining signal synchronization through the feedback loop.
3Reliability
If conventional DLL design is used, then the circuit can provide delay-lock functionality, but circuit area is larger and distortion is higher
Solution Approach 1:
The patent merges the delay-line functionality with a voltage-controlled oscillator and loop filter into a single integrated circuit. This consolidation eliminates the need for separate tap-controlled delay line components, reducing overall circuit area while maintaining delay-lock functionality through the VCO's phase control capability.
4Productivity
If conventional DLL design is used, then the output signal can be generated, but duty cycle errors and distortion are introduced
Solution Approach 1:
The patent employs a feedback loop that monitors the output signal and adjusts the VCO control voltage to maintain accurate duty cycle. The loop filter processes error signals and provides corrective voltage adjustments, eliminating duty cycle errors and distortion that would otherwise be introduced by the frequency multiplication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces circuit area, minimizes distortion, and eliminates duty cycle errors, providing a stable and programmable frequency multiplication with reduced noise and spurs in the output clock signal.
Implementation Method 1
The VCO, which includes an input to receive a control voltage and an output to generate an oscillation output signal, adjusts the frequency of the oscillation output signal in response to the control voltage
Implementation Method 2
The charge pump, which is coupled to the phase detector, generates a control voltage in response to the UP and DN control signals
Implementation Method 3
The phase detector, which includes inputs to receive a reference signal and a feedback signal, generates UP and DN control signals in response to a phase difference between the reference signal and the feedback signal
Data Source
AI summary
A charge pump circuit is disclosed that includes a main charge pump, a replica charge pump, and an op-amp. The main charge pump includes up and down input terminals to receive UP and DN control signals, a control terminal to receive a calibration signal, and an output to generate a control voltage. The replica charge pump includes up and down input terminals to receive DN and UP control signals, a control terminal to receive the calibration signal, and an output to generate a replica voltage. The op-amp generates the calibration signal in response to the control voltage and the replica voltage.