Charge Pump Deep N-Well Biasing for Parasitic Junction Control
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Solution Overview
Problem
Charge pumps used in flash memory face challenges in activating parasitic PN-junctions or transistors when bias voltage is changed, requiring effective biasing schemes to prevent unwanted activation during positive and negative pump operations.
Innovation Solution
A deep N-well biasing scheme is implemented for NMOS devices in charge pump stages, where the deep N-well is floated during positive pump operations and coupled to ground during negative pump operations, using specific voltage levels to ensure the parasitic PN junctions remain off, employing a 4-phase charge pump stage with clock signals and NMOS switches to manage the biasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If bias voltage is changed for desired operation in charge pump, then the charge pump can switch between positive and negative pump operations, but parasitic PN-junction or transistor structure may be activated causing unwanted effects
Solution Approach 1:
A deep N-well structure is introduced as an intermediary element between the P-well and substrate. The deep N-well acts as a mediator to provide an additional reverse bias path for the parasitic PN-junction, preventing its activation during voltage transitions while allowing the charge pump to switch between positive and negative pump operations
2Reliability
If deep N-well is floated during positive pump operation, then parasitic PN junction remains off, but deep N-well needs to be coupled to ground during negative pump operation to prevent activation
Solution Approach 1:
The biasing configuration of the deep N-well is made dynamic rather than static. The deep N-well is connected to different voltage potentials (floating during positive pump operation, coupled to ground during negative pump operation) depending on the operational mode, allowing reliable parasitic junction suppression while adapting to different operating conditions
Data Source
AI summary
A charge pump has at least one charge pump stage. Each charge pump stage includes at least one NMOS device. The at least one NMOS device has a deep N-well (DNW), and is coupled to at least one capacitor, an input node, and an output node. The input node is arranged to receive an input signal. The at least one capacitor is arranged to store electrical charges. The charge pump stage is configured to supply the electrical charges to the output node, and the DNW is arranged to float for a positive pump operation.