Charge Pump Doubler With Localized Gate Oxide Thickness
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Solution Overview
Problem
Conventional charge pump circuits face degradation in pump driving capability due to low power supply voltage, low temperature, or high threshold voltage of MOS transistors with thick gate oxide, leading to inefficient voltage doubling and current backflow, which affects the output voltage efficiency.
Innovation Solution
The charge pump doubler circuit selectively uses PMOS and NMOS transistors with thicker gate oxides for high voltage endurance and devices with similar gate oxide thickness for logic devices, along with MOS capacitors and diode-connected transistors to maintain voltage differences within manageable limits, enabling efficient voltage doubling and improved current driving capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MOS transistors with thick gate oxide are used to endure high voltage stress, then voltage endurance is improved, but threshold voltage increases and pump driving capability degrades
Solution Approach 1:
The patent applies different gate oxide thicknesses to different transistor locations based on their specific voltage stress requirements. Transistors experiencing high voltage stress (first and second PMOS transistors) use thick gate oxide for reliability, while transistors with lower stress (third PMOS transistor and logic devices) use thinner gate oxide to maintain lower threshold voltage and better driving capability. This localized differentiation resolves the contradiction between voltage endurance and pump driving capability.
2Use of energy by moving object
If low power supply voltage is used, then power consumption is reduced, but pump driving capability degrades and voltage doubling efficiency decreases
Solution Approach 1:
The patent changes the gate oxide thickness parameter of transistors to compensate for low power supply voltage effects. By using thick gate oxide transistors in critical high-stress positions, the circuit maintains stable voltage doubling performance even at low supply voltages, preventing the degradation of pump driving capability while keeping power consumption low.
3Reliability
If thick gate oxide transistors are used throughout the circuit, then voltage stress resistance is improved, but threshold voltage increases and current driving capability decreases
Solution Approach 1:
The patent implements local quality by selectively placing thick gate oxide transistors only where high voltage stress occurs (first PMOS transistor connected to doubled output voltage, second PMOS transistor in charge pump path), while using thinner gate oxide for other transistors. This ensures voltage stress resistance is improved where needed without unnecessarily increasing threshold voltage and reducing current driving capability throughout the entire circuit.
Data Source
AI summary
An integrated circuit includes a first PMOS transistor, where its drain is arranged to be coupled to a voltage output, and its source is coupled to the drain of a second PMOS transistor. The source of the second PMOS transistor is arranged to be coupled to a high power supply voltage. The source and drain of a MOS capacitor are coupled to the source of the first PMOS transistor. The drain of an NMOS transistor is coupled to the drain of the first PMOS transistor. The integrated circuit is configured to receive a voltage input to generate the voltage output having a maximum voltage higher than the voltage input. The gate oxide layer thickness of the MOS capacitor is less than that of the first PMOS transistor.