Charge Pump Duty Cycle Correction for DDR Clock Timing
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Solution Overview
Problem
Existing duty cycle correction circuits in synchronous semiconductor memory devices, such as DDR SDRAM, are complex and require a large silicon area, and they struggle to respond quickly to variations in process, supply voltage, and temperature, leading to timing and noise issues that affect data transmission reliability.
Innovation Solution
A duty cycle correction circuit comprising a duty cycle detector, filter, amplifier, charge pump, control circuit, and duty cycle corrector that generates control signals to adjust internal clock signals to a corrected duty cycle, using a charge pump with adjustable bias current to quickly respond to duty cycle variations while minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a digital duty cycle correction circuit with counter and DAC is used, then the duty cycle can be corrected, but the circuit becomes complex and requires large silicon area
Solution Approach 1:
The patent replaces the digital correction mechanism (counter and DAC) with an analog correction mechanism using a charge pump circuit. The charge pump continuously adjusts the duty cycle of internal clock signals by transferring charge between capacitors in response to detection signals, eliminating the need for complex digital components while achieving precise duty cycle correction.
Solution Approach 2:
The duty cycle correction circuit operates autonomously through feedback. The duty cycle detector continuously monitors the internal clock signals and generates detection signals that automatically control the charge pump to adjust the duty cycle, creating a self-regulating system that maintains 50% duty cycle without external intervention.
2Productivity
If the operational speed of DDR SDRAM is increased, then data transmission speed improves, but timing and noise problems worsen and design margin decreases
Solution Approach 1:
The patent implements a feedback mechanism where the duty cycle detector continuously monitors the actual duty cycle of internal clock signals and feeds detection signals back to the charge pump. This closed-loop control ensures that the duty cycle remains precisely at 50% even at high operational speeds, maintaining timing integrity and reducing noise effects that would otherwise worsen with increased speed.
Solution Approach 2:
The charge pump dynamically adjusts the duty cycle parameter of internal clock signals in real-time by transferring charge between capacitors. This continuous parameter adjustment compensates for process, voltage, and temperature variations, ensuring stable timing performance and reduced noise sensitivity even as operational speed increases.
3Reliability
If a duty cycle correction circuit is added to DLL, then data transmission reliability improves, but the circuit complexity and silicon area increase
Solution Approach 1:
The patent replaces complex digital correction circuitry with a compact analog charge pump implementation. The charge pump uses simple charge transfer between capacitors controlled by detection signals, achieving duty cycle correction with minimal circuit complexity and small silicon area while integrating seamlessly into the DLL structure.
Solution Approach 2:
The patent introduces a duty cycle detector as an intermediary component that bridges the external clock signal and the internal clock signal generation. The detector monitors the internal clock signals and generates detection signals that mediate the correction process, enabling reliable duty cycle control without adding significant complexity to the overall DLL architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a simplified and efficient duty cycle correction mechanism that rapidly adjusts internal clock signals to achieve a desired 50% duty cycle, improving data transmission reliability and reducing power consumption by operating in both linear and saturation regions effectively.
Implementation Method 1
The charge pump is configured to generate a second pair of control signals according to the enable signal and the selection signal
Data Source
AI summary
A duty cycle correction circuit comprises a duty cycle detector, a filter, an amplifier, a charge pump, a control circuit, and a duty cycle corrector. The duty cycle detector is configured to generate a first pair of control signals according to a pair of internal clock signals. The filter is configured to obtain average voltages of the first pair of control signals. The amplifier is configured to compare output voltages of the filter for generating an enable signal, and the control circuit is configured to generate a selection signal according to the enable signal. The charge pump is configured to generate a second pair of control signals according to the enable signal and the selection signal, and the duty cycle corrector is configured to receive a pair of external clock signals, the first pair of control signals, and the second pair of control signals for generating the pair of internal clock signals with a corrected duty cycle.