Charge Pump Circuit Dynamic Frequency Control
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Solution Overview
Problem
Existing charge pump circuits face challenges in reducing power consumption while maintaining efficient voltage regulation, often resulting in high power loss and complex circuit configurations due to the need for frequent frequency adjustments and increased current control accuracy.
Innovation Solution
A charge pump circuit that includes a clock generator with varying frequency and a voltage raiser, where the frequency of the clock signal is adjusted based on the output voltage and load current, using a CR oscillator or ring oscillator with inverters, and a clock generator controller to manage the frequency control current, thereby simplifying the circuit configuration and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the clock signal frequency is constantly adjusted to match load requirements, then power consumption is reduced, but the circuit complexity increases due to frequent frequency adjustments and current control requirements
Solution Approach 1:
The patent implements dynamic frequency adjustment of the clock signal based on load detection. The oscillation frequency changes from a first frequency (when load current is below threshold) to a second frequency (when load current exceeds threshold), allowing the system to adapt to varying power requirements while maintaining simple circuit architecture through predetermined frequency switching rather than continuous control
Solution Approach 2:
The patent changes the frequency parameter of the clock signal in response to load conditions. By detecting whether the load current exceeds a predetermined threshold value and switching between two frequency states, the system achieves power consumption optimization without requiring complex continuous control mechanisms
2Area of stationary object
If an NMOS transistor is used as high-side switching device, then area and production cost are reduced, but a voltage raising circuit is required to drive the gate, increasing current consumption and withstand voltage requirements
Solution Approach 1:
The patent uses periodic clock signals to control the NMOS transistor switching. The transistor operates in periodic switching cycles rather than remaining continuously ON, which reduces average current consumption while maintaining the area advantages of NMOS devices. The periodic action allows the transistor to handle high voltage requirements only during brief switching intervals
Solution Approach 2:
The patent introduces a voltage raising circuit that generates a boosted voltage to drive the NMOS gate. This intermediary circuit enables the NMOS transistor to function as a high-side switch by providing the necessary gate drive voltage, while the transistor itself remains area-efficient. The voltage raiser acts as a mediator that resolves the conflict between using small-area NMOS devices and meeting gate drive voltage requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves power saving by dynamically adjusting the clock signal frequency in response to output voltage and current levels, reducing unnecessary power consumption and simplifying the circuit design, making it suitable for compact mobile devices.
Implementation Method 1
a voltage raiser configured to generate a raised output voltage higher than a supplied input voltage by using the clock signal
Data Source
AI summary
When a voltage difference between a raised output voltage vcp and an input voltage vin is larger than a set voltage value, based on a added-on voltage vup detected by a voltage monitor 3 or a current iu passing through the voltage monitor 3, the clock generator controller 4 is activated. Then the clock generator controller 4 draws in a frequency control current iw from a clock generator 1 side, switches the frequency Fclk of a clock signal CLK generated by the clock generator 1 from a first frequency, which is comparatively high, to a second frequency, which is one or more digits lower than the first frequency, and applies the clock signal CLK to the voltage raiser 2. The voltage raiser 2 saves power by performing voltage raising (charge pumping) at the second frequency.